Step 4: Turning Off Optimizations on Specific Signals and Rerunning the Implementation - 2024.1 English

Vivado Design Suite Tutorial: Power Analysis and Optimization (UG997)

Document ID
UG997
Release Date
2024-05-30
Version
2024.1 English
In this step you will learn how to turn off the power optimization on specific block RAMs.
Important: Power optimization works to minimize the impact on timing while maximizing power savings. However, in certain cases, if timing degrades after power optimization, you can identify and apply power optimizations only on non-timing critical clock domains or modules using the set_power_opt XDC command.

See the Vivado Design Suite User Guide: Power Analysis and Optimization (UG907) for more information on the set_power_opt command.

There are no tool gated blocks in this design, but assume that this block RAM is in the critical path:

dut/Cascaded_bram/gen_dut[0].bram_top_cascade/bram_cas/mem_reg_bram_0

This step makes sure the tool does not gate this block RAM.

  1. In the Tcl Console, type this command:
    set_power_opt -exclude_cells [get_cells dut/Cascaded_bram/gen_dut[0].bram_top_cascade/bram_cas/mem_reg_bram_0]

    This prevents the tool from gating this block RAM.

  2. From the Flow Navigator choose Run Implementation, which in turn reruns power_opt_design.
  3. Click Save in the Save Project dialog box to save the synthesized design and implemented design constraints before launching implementation.
    Click OK on the Save Constraints dialog box to save the changes in constraints from the set_power_opt command.

  4. In the Implementation Completed dialog box, select Open Implemented Design and click OK.