Tutorial Design Description - 2024.1 English

Vivado Design Suite Tutorial: Design Flows Overview (UG888)

Document ID
UG888
Release Date
2024-05-30
Version
2024.1 English

The sample design used throughout this tutorial consists of a small design called bft. There are several VHDL and Verilog source files in the bft design, as well as a XDC constraints file. The design targets an xc7k70T device. A small design is used to allow the tutorial to be run with minimal hardware requirements and to enable timely completion of the tutorial, as well as to minimize the data size.