Using the Project Design Flow - 2024.1 English

Vivado Design Suite Tutorial: Design Flows Overview (UG888)

Document ID
UG888
Release Date
2024-05-30
Version
2024.1 English

In this lab, you will learn about the Project mode features for project creation, source file management, design analysis, constraint definition, and synthesis and implementation run management.

You will walk through the entire FPGA design flow using an example design, starting in the AMD Vivado™ IDE. Then you will examine some of the major features in the IDE. Most of these features are covered in detail in other tutorials. Finally, you will create a batch run script to implement the design project and see how easy it is to switch between running Tcl scripts and working in the Vivado IDE.