Analyze Routing - 2024.1 English

Vivado Design Suite Tutorial: Design Flows Overview (UG888)

Document ID
UG888
Release Date
2024-05-30
Version
2024.1 English

After the design has been placed and routed, you can generate a timing report to verify that all the timing constraints are met. You can select paths from the Timing Report window to examine the routed path in the Device window. If there are timing problems, you can revisit the RTL source files or design constraints to address any problems.

  1. In the Device window, select the Routing Resources button to display the device routing.

    This lets you see the routed connection in the Device window. Though you will need to zoom closely into the device to see elements of the route, a zoomed-out view lets you see the route in its entirety.

  2. Select the Auto-fit Selection button in the Device window toolbar menu to enable the Vivado IDE to automatically zoom into and center the selected objects.
  3. On the left side pane of the Timing window, select Intra-Clock Paths > wbClk > HOLD
  4. In the table view on the right side of the Timing Summary Report window, click any timing path to select it and highlight it in the Device window. Select various paths in the Timing Summary window and examine the path routing. The waveform button above the timing path allows you to enable or disable the clocking portion of the timing path.
  5. On the left side pane of the Timing Summary Results window, select Intra-Clock Paths > wbClk > SETUP.
  6. Click any path in the table view on the right side of the Timing Summary Results window to select it and highlight it in the Device window. Select various paths in the Timing Summary Results window and examine the path routing.