- Examine the information in the Project Summary. More detailed information is presented as the design progresses through the design flow.
- Examine the Sources window and expand the Design
Sources, Constraints and
Simulation Sources folders.
The Design Sources folder helps keep track of VHDL and Verilog source files and libraries. Notice the Hierarchy tab displays by default.
- Select the Libraries tab and the Compile
Order tabs in the Sources window and notice the different ways
that sources are listed.
The Libraries tab groups source files by file type. The Compile Order tab shows the file order used for synthesis.
- Expand the various folders to view the design source information.
- Select the Hierarchy tab.