Resets - 1.3 English

DPUCVDX8G for Versal ACAPs Product Guide (PG389)

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1.3 English

There are two input clocks for the DPUCVDX8G PL, and each clock has a corresponding reset. Each reset must be synchronous to its corresponding clock. If the related clocks and resets are not synchronized, the DPUCVDX8G might not work properly.

The output clock on the AI Engine component does not have a corresponding reset signal.