Port Description - 1.3 English

DPUCVDX8G for Versal ACAPs Product Guide (PG389)

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1.3 English

Ports are available from the DPUCVDX8G to the NoC and the PS. The interface from the PS to the DPUCVDX8G PL component is used for register configuration. The interfaces from the DPUCVDX8G PL component to the NoC are for image and weight transfers. The interfaces from the PL component to the AI Engine component are for intermediate data exchange.

Figure 1. Connections from DPUCVDX8G to PS and NoC

There are parameters to configure the DPUCVDX8G architecture. The data width and number of different DPUCVDX8G interfaces differs for each architecture. The DPUCVDX8G IP catalog with C32B1CU1 (CPB_N=32, CU_N=1) architecture is shown in the following figure:

Figure 2. DPUCVDX8G Ports with C32B1CU1 Architecture