Peak Theoretical Performance Metrics - Peak Theoretical Performance Metrics - 1.3 English - PG389

DPUCVDX8G for Versal ACAPs Product Guide (PG389)
Document ID
PG389
Release Date
2023-01-23
Version
1.3 English

The following table shows the peak theoretical performance of the DPUCVDX8G with 15 architectures. These metrics assume a 333 MHz PL frequency and 1.25 GHz AI Engine frequency.

Table 1. Peak Theoretical Performance of the DPUCVDX8G
Architecture Peak Theoretical Performance (TOPS)
C32B1CU1L2S2 10.24
C32B1CU2L2S2 20.48
C32B1CU3L2S2 30.72
C32B2CU1L2S2 20.48
C32B3CU1L2S2 30.72
C32B4CU1L2S2 40.96
C32B5CU1L2S2 51.20
C32B6CU1L2S2 61.44
C64B1CU1L2S2 20.48
C64B1CU2L2S2 40.96
C64B1CU3L2S2 61.44
C64B2CU1L2S2 40.96
C64B3CU1L2S2 61.44
C64B4CU1L2S2 81.92
C64B5CU1L2S2 102.4
  1. The peak number of operations per clock cycle of a single AI Engine core is 256. Thus, the total peak theoretical performance is calculated as 256 * CPB_N * BATCH_N * CU_N * AI Engine Frequency, where:
    • CPB_N is the number of AI Engines per batch handler (C64)
    • BATCH_N is the maximum batch size (B5)
    • CU_N is the number of CUs for a specific DPU architecture (1)

    Example: C64B5CU1L2S2

    Peak TOPs = 256 * 64 * 5 * 1 * 1.25 GHz

    Peak TOPs = 102.4