Read Latency Calibration - 1.0 English

Versal ACAP Soft RLDRAM 3 Memory Controller LogiCORE IP Product Guide (PG354)

Document ID
PG354
Release Date
2021-11-03
Version
1.0 English
Read latency calibration involves two steps. The first step determines the read bitslip value and the second step determines the read latency value.
  1. The read bitslip value is set to zero and the read latency is set to a large value so that read data is properly read. A unique write data pattern is written to different bank addresses. These addresses are read back continuously. Adjust the bitslip of each nibble until the read data matches the expected pattern.
  2. Once the correct read bitslip is determined, set the read latency value to zero. Read once from the same address and compare with expected pattern. If not matched, then increase the read latency by 1. Repeat until read data matches expected data thereby completing read latency calibration.