- Verify that the system clock frequency on hardware matches the IP setting (Input
System Clock Period).
- Verify all guidelines in the Memory Interface chapter of the
Versal ACAP PCB Design User Guide (UG863) have been followed.
- Check the rules on the pin and bank options in RLDRAM 3 Memory Controller (see Pin and Bank Rules).
- Measure voltages on the board during idle and non-idle times to ensure the
voltages are set appropriately and the noise is within specifications.
- Ensure the termination voltage regulator (VTT) is powered to
VCCO/2.
- Scope the clock input to verify frequency and signal quality.
- Check the termination registers for the proper values. These are detailed in
the Memory Interface chapter of the
Versal ACAP PCB Design User Guide (UG863).
- Perform general signal integrity analysis:
- Observe
dq
, dk_p/n
, and qk_p/n
signals using a scope at the memory. View the alignment of the signals
and the VIL/VIH
levels during both reads and writes and the overall signal
integrity.
- Observe the Address and Command signals on a scope at the memory. View
the alignment of the signals and the VIL/VIH
levels and the overall signal integrity.
- Verify the memory parts on the board match the settings set in the Memory IP.
The timing parameters must match between the IP and the physical part.
- Measure
ck_p/n
, dk_p/n
,
qk_p/n
and the system clock for duty cycle distortion and
general signal integrity.
- Verify timing constraint rules (trace matching) are being met as documented
in the Memory Interface chapter of the
Versal ACAP PCB Design User Guide (UG863).