The Memory Controller (MC) enforces the RLDRAM 3 access requirements like the Row Cycle time (tRC) and Write to Read time (tWTR) while keeping the throughput as high as possible. The Memory Controller also interfaces with the PHY.
Commands are reordered in the command queue by the controller based on the Row Cycle time (tRC) of the commands. For example, a command whose tRC is met is scheduled before a command whose tRC is not met thereby improving throughput of the interface. Another command reorder module reorders the position of the write and read commands in a single user cycle. This feature is mostly useful for BL2. With BL2, four commands are issued in a single user clock cycle. For example, if the four commands are Write, Read, Write, and Read with the last command of the previous user clock as Write, then the new arrangement of commands will be Read, Read, Write, and Write.
The MC features a read command bypass mode which is supported when
Data Mask (DM) is disabled by setting the top-level parameter DM_EN to 0. This feature
improves throughput by bypassing a read command that follows a write command to the same
address. In this scenario, the write data associated with the write command can be
driven to the user_rd_data port thereby saving tWTR (WL
+ BL / 2) wait time and the read command execution time. The MC command execution
sequence is different from the command request order in the user interface. Therefore,
the read response is reordered to match the command request order at the user
interface.
Auto-refresh commands are inserted into the command flow by the MC to meet the memory device refresh requirements. CMD_PER_CLK is a top-level parameter used to determine how many memory commands are provided to the MC per Versal ACAP logic clock cycle. The number of memory commands per Versal ACAP logic clock cycle depends on the burst length. For example, the CMD_PER_CLK is set to 1 for burst length = 8, CMD_PER_CLK is set to 2 for burst length = 4, and CMD_PER_CLK is set to 4 for burst length = 2.