Versal ACAP Soft RLDRAM 3 Memory Controller LogiCORE IP Product Guide (PG354) - 1.0 English - Describes the Xilinx® Versal® ACAP soft RLDRAM 3 memory controller IP core which is a combined pre-engineered controller and physical layer (PHY) for interfacing Versal ACAP user designs to RLDRAM 3 devices. - PG354

Document ID

PG354

Release Date

2021-11-03

Version

1.0 English