RLDRAM 3 Pinout Examples - 1.0 English

Versal ACAP Soft RLDRAM 3 Memory Controller LogiCORE IP Product Guide (PG354)

Document ID
PG354
Release Date
2021-11-03
Version
1.0 English
Important: Due to the calibration stage, set_input_delay/set_output_delay on the RLDRAM 3 is not necessary. Ignore the unconstrained inputs and outputs for RLDRAM 3 and the signals which are calibrated.