| AMD LogiCORE™ IP Facts Table | |
|---|---|
| Subsystem Specifics | |
| Supported Device Family 1 |
AMD UltraScale+™
Note: This solution is targeted to U200, U250, U280, U50, U55, U45N, X3, and UL3524
Alveo cards.
|
| Supported User Interfaces | AXI4-Lite |
| Resources | Performance and Resource Use web page |
| Provided with Subsystem | |
| Design Files | IP integrator HIP Subsystem |
| Example Design | VHDL/Verilog |
| Test Bench | N/A |
| Constraints File | Xilinx Design Constraints (XDC) |
| Simulation Model | N/A |
| Supported S/W Driver | N/A |
| Tested Design Flows 2 | |
| Design Entry | AMD Vivado™ Design Suite |
| Simulation | N/A. |
| Synthesis | N/A |
| Support | |
| All Vivado IP Change Logs | Master Vivado IP Change Logs: Answer Record 72775 |
| Support web page | |
|
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