MAILBOX Offset | 32-bit Word | Field Type | Field Description |
---|---|---|---|
0x00
|
[0] | Host Request Message | Message Header 31:24
Opcode ( 23:0 Reserved |
0x04
|
[1] | Host Request Message | Cage Select (0-1) |
0x08
|
[2] | Host Request Message | Low Speed I/O Write Data
1, 2
QSFP Module 31-2: Reserved 1: QSFP_LPMODE (0: High Power Mode, 1: Low Power Mode) 0: QSFP_RESET_L (0: Reset Active, 1: Reset Clear) DSFP Module Low Speed I/O Read Data - DSFP Module31-2: Reserved 1: DSFP_LPW (0: High Power Mode, 1: Low Power Mode) 0: DSFP_RST (0: Reset Clear, 1: Reset Active) SFP+ Module Low Speed I/O Read Data - SFP+ Module31-0: Reserved |
|
Host Action | Function |
---|---|
Peek 0x28018
|
Check availability of the Mailbox by confirming CONTROL_REG[5] is 0 |
Poke 0x29000
0x0E000000
|
Write Request Message Header into MAILBOX Word
0 (Opcode). Assumes HOST_MSG_OFFSET_REG = 0x1000. |
Poke 0x29004
0x00000000
|
Select Cage 0 |
Poke 0x29008
0x00000000
|
Set QSFP Low speed Write Data. Write 0 to QSFP_RESET_L to trigger a QSFP module reset. |
Poke 0x28018
0x20
|
Set CONTROL_REG[5] to 1 to indicate a new request message is available. |
Peek 0x28018
|
Poll CONTROL_REG bit 5 until ‘0’ is received indicating CMS has completed write operation. |
Peek 0x28304
|
Confirm no errors in HOST_MSG_ERR_REG. |
Host Action | Function |
---|---|
Peek 0x28018
|
Check availability of the Mailbox by confirming CONTROL_REG[5] is 0 |
Poke 0x29000
0x0E000000
|
Write Request Message Header into MAILBOX Word
0 (Opcode). Assumes HOST_MSG_OFFSET_REG = 0x1000. |
Poke 0x29004
0x00000001
|
Select Cage 1 |
Poke 0x29008
0x00000001
|
Set DSFP Low speed Write Data. Write 1 to DSFP_RST to hold DSFP module in reset. |
Poke 0x28018
0x20
|
Set CONTROL_REG[5] to 1 to indicate a new request message is available. |
Peek 0x28018
|
Poll CONTROL_REG bit 5 until ‘0’ is received indicating CMS has completed write operation. |
Peek 0x28304
|
Confirm no errors in HOST_MSG_ERR_REG. |