This table shows the AXI Memory Init IP Slave Interface signals.
| Signals | I/O | Default | Width | Description |
|---|---|---|---|---|
| s_axi_awid | I | AXI3, AXI4: 0 | ID_WIDTH | Write Address Channel Transaction ID |
| s_axi_awaddr | I | REQ | ADDR_WIDTH | Write Address Channel Address |
| s_axi_awlen | I | AXI3, AXI4: 0 |
AXI4: 8 AXI3: 4 |
Write Address Channel Burst Length (0–255) |
| s_axi_awsize | I |
AXI3, AXI4: REQ |
3 | Write Address Channel Transfer Size Code (0–7) |
| s_axi_awburst | I |
AXI3, AXI4: REQ |
2 | Write Address Channel Burst Type Code (0–2). |
| s_axi_awlock | I | AXI3, AXI4: 0 |
AXI4: 1 AXI3: 2 |
Write Address Channel Atomic Access Type (0, 1) |
| s_axi_awcache | I | AXI3, AXI4: 0 | 4 | Write Address Channel Cache Characteristics |
| s_axi_awprot | I | 0b000 | 3 | Write Address Channel Protection Bits |
| s_axi_awqos | I | AXI4: 0 | 4 | AXI4 Write Address Channel Quality of Service |
| s_axi_awregion | I | AXI4: 0; AXI3: d/c | 4 | AXI4 Write Address Channel Address Region Index |
| s_axi_awuser | I | AXI3, AXI4: 0 | AWUSER_WIDTH | User-defined AW Channel Signals |
| s_axi_awvalid | I | REQ | 1 | Write Address Channel Valid |
| s_axi_awready | O | 1 | Write Address Channel Ready | |
| s_axi_wid | I |
AXI3: 0 AXI4: d/c |
ID_WIDTH | Write Data Channel Transaction ID for AXI3 Masters |
| s_axi_wdata | I | REQ | DATA_WIDTH | Write Data Channel Data |
| s_axi_wstrb | I | All ones | DATA_WIDTH/8 | Write Data Channel Byte Strobes |
| s_axi_wlast | I | AXI3, AXI4: 0 | 1 | Write Data Channel Last Data Beat |
| s_axi_wuser | I | AXI3, AXI4: 0 | WUSER_WIDTH | User-defined W Channel Signals |
| s_axi_wvalid | I | REQ | 1 | Write Data Channel Valid |
| s_axi_wready | O | 1 | Write Data Channel Ready | |
| s_axi_bid | O | ID_WIDTH | Write Response Channel Transaction ID | |
| s_axi_bresp | O | 2 | Write Response Channel Response Code (0–3) | |
| s_axi_buser | O | BUSER_WIDTH | User-defined B Channel Signals | |
| s_axi_bvalid | O | 1 | Write Response Channel Valid | |
| s_axi_bready | I | REQ | 1 | Write Response Channel Read |
| s_axi_arid | I | AXI3, AXI4: 0 | ID_WIDTH | Read Address Channel Transaction ID |
| s_axi_araddr | I | REQ | ADDR_WIDTH | Read Address Channel Address |
| s_axi_arlen | I | AXI3, AXI4: 0 |
AXI4: 8 AXI3: 4 |
Read Address Channel Burst Length code (0–255) |
| s_axi_arsize | I | AXI3, AXI4: REQ | 3 | Read Address Channel Transfer Size Code (0–7) |
| s_axi_arburst | I | AXI3, AXI4: REQ | 2 | Read Address Channel Burst Type (0–2) |
| s_axi_arlock | I | AXI3, AXI4: 0 |
AXI4: 1 AXI3: 2 |
Read Address Channel Atomic Access Type (0, 1) |
| s_axi_arcache | I | AXI3, AXI4: 0 | 4 | Read Address Channel Cache Characteristics |
| s_axi_arprot | I | 0b000 | 3 | Read Address Channel Protection Bits |
| s_axi_arregion | I | AXI4: 0; AXI3: d/c | 4 | AXI4 Read Address Channel Address Region Index |
| s_axi_arqos | I | AXI4: 0 | 4 | AXI4 Read Address Channel Quality of Service |
| s_axi_aruser | I | AXI3, AXI4: 0 | ARUSER_WIDTH | User-defined AR Channel Signals |
| s_axi_arvalid | I | REQ | 1 | Read Address Channel Valid |
| s_axi_arready | O | 1 | Read Address Channel Ready | |
| s_axi_rid | O | ID_WIDTH | Read Data Channel Transaction ID | |
| s_axi_rdata | O | DATA_WIDTH | Read Data Channel Data | |
| s_axi_rresp | O | 2 | Read Data Channel Response Code (0–3) | |
| s_axi_rlast | O | 1 | Read Data Channel Last Data Beat | |
| s_axi_ruser | O | RUSER_WIDTH | User-defined R Channel Signals | |
| s_axi_rvalid | O | 1 | Read Data Channel Valid | |
| s_axi_rready | I | REQ | 1 | Read Data Channel Ready |