When the AXI Memory Init core is in its initial state, it is in Initialization Mode. The AXI Memory Init IP immediately re-enters Initialization Mode following a reset.
During Initialization Mode, the slave interface (SI) of the core is held in a
quiescent state for write and read. No write or read commands requested on the SI are accepted
(s_axi_awready and s_axi_arready output signals are deasserted). No write responses received on the
master interface (MI) are propagated to the SI. Any read data transfers observed on the MI are
ignored, as AXI protocol prohibits them from occurring when no read commands have been
issued.
While in the Initialization Mode, the AXI Memory Init IP autonomously writes an initial value (default all-zeros) to all
specified address locations accessible on the MI, according to the values of BASE_ADDR and
ADDR_SIZE. That is, the IP assumes that the memory to be initialized is of size 2**ADDR_SIZE
bytes. Throughout Initialization Mode, init_complete_out is
driven to zero.
After writing all locations and waiting for all outstanding write responses (which are accepted and discarded), the IP transitions to Operational Mode.
For all write transactions issued autonomously during Initialization Mode:
- AWLEN =
h'0F(16-beat bursts) - AWSIZE = log2(DATA_WIDTH / 8), that is, full-width
- AWBURST =
2'h01(INCR) - AWID, AWPROT, AWCACHE, AWQOS, AWUSER, AWLOCK = all zeros
- WDATA = INIT_VALUE
- WSTRB = all ones
- WUSER = all zeros
For the first write transaction, AWADDR = BASE_ADDR. For each subsequent write transaction issued, AWADDR is incremented by 16 * (DATA_WIDTH / 8).