Interface Ports - 1.1 English - PG337

Soft ECC Proxy LogiCORE IP Product Guide (PG337)
Document ID
PG337
Release Date
2023-11-01
Version
1.1 English
Table 1. Interface Ports
Port Name I/O Width Description
s_aclk I 1 Global Slave Interface Clock. All signals are sampled on the rising edge of this clock.
s_aresetn I 1 Active-Low asynchronous reset
AXI4-Lite Interface
s_axil_awaddr I 32 AXI4-Lite Write Address
s_axil_awprot I 3 AXI4-Lite Write Protection Type
s_axil_awvalid I 1 AXI4-Lite Write Address Valid
s_axil_awready O 1 AXI4-Lite Write Address Ready
s_axil_wdata I 32 AXI4-Lite Write Data
s_axil_wstrb I 4 AXI4-Lite Write Strobe
s_axil_wvalid I 1 AXI4-Lite Write Data Valid
s_axil_wready O 1 AXI4-Lite Write Data Ready
s_axil_bresp O 2 AXI4-Lite Write Response
s_axil_bvalid O 1 AXI4-Lite Write Response Valid
s_axil_bready I 1 AXI4-Lite Write Response Ready
s_axil_araddr I 32 AXI4-Lite Read Address
s_axil_arprot I 3 AXI4-Lite Read Protection Type
s_axil_arvalid I 1 AXI4-Lite Read Address Valid
s_axil_arready O 1 AXI4-Lite Read Address Ready
s_axil_rdata O 32 AXI4-Lite Read Data
s_axil_rresp O 2 AXI4-Lite Read Response
s_axil_rvalid O 1 AXI4-Lite Read Data Valid
s_axil_rready I 1 AXI4-Lite Read Data Ready
AXI4-Lite - MM Slave Interface (Write Address Channel)
s_axi_awid I C_ID_WIDTH Write Address ID. Identification tag for the write address group of signals.
s_axi_awaddr I C_ADDR_WIDTH Write Address. The write address bus gives the address of the first transfer in a write burst transaction. The associated control signals are used to determine the addresses of the remaining transfers in the burst.
s_axi_awlen I 8 Burst Length. The burst length gives the exact number of transfers in a burst. This information determines the number of data transfers associated with the address.
s_axi_awsize I 3 Burst Size. Indicates the size of each transfer in the burst. Byte lane strobes indicate exactly which byte lanes to update.
s_axi_awburst I 2 Burst Type. The burst type, coupled with the size information, details how the address for each transfer within the burst is calculated.
s_axi_awlock I 2 Lock Type. This signal provides additional information about the atomic characteristics of the transfer.
s_axi_awcache I 4 Cache Type. Indicates the buffer-able, cache-able, write-through, write-back, and allocate attributes of the transaction.
s_axi_awprot I 3 Protection Type. Indicates the normal, privileged, or secure protection level of the transaction and whether the transaction is a data access or an instruction access.
s_axi_awqos I 4 Quality of Service (QoS). Sent on the write address channel for each write transaction.
s_axi_awregion I 4 Region Identifier. Sent on the write address channel for each write transaction.
s_axi_awuser I C_AWUSER_WIDTH Write Address Channel User
s_axi_awvalid I 1 Write Address Valid. Indicates that valid write address and control information are available.
s_axi_awready O 1 Write Address Ready. Indicates that the slave is ready to accept an address and associated control signals.
AXI4-Lite - MM Slave Interface (Write Data Channel)
s_axi_wdata I C_DATA_WIDTH Write Data. The write data bus can be 8, 16, 32, 64, 128, 256, or 512 bits wide.
s_axi_wstrb I C_DATA_WIDTH/8 Write Strobes. Indicates which byte lanes to update in memory. There is one write strobe for each eight bits of the write data bus.
s_axi_wlast I 1 Write Last. Indicates the last transfer in a write burst.
s_axi_wuser I C_WUSER_WIDTH Write Data Channel User
s_axi_wvalid I 1 Write Valid. Indicates that valid write data and strobes are available.
s_axi_wready O 1 Write Ready. Indicates that the slave can accept the write data.
AXI4-Lite - MM Slave Interface (Write Response Channel)
s_axi_bid O C_ID_WIDTH Response ID. The identification tag of the write response. The BID value must match the AWID value of the write transaction to which the slave is responding.
s_axi_bresp O 2 Write Response. Indicates the status of the write transaction. The allowable responses are OKAY, EXOKAY, SLVERR, and DECERR.
s_axi_buser O C_BUSER_WIDTH Write Response Channel User
s_axi_bvalid O 1 Write Response Valid. Indicates that a valid write response is available.
s_axi_bready I 1 Response Ready. Indicates that the master can accept the response information.
AXI4-Lite - MM Slave Interface (Read Address Channel)
s_axi_arid I C_ID_WIDTH Read Address ID. This signal is the identification tag for the read address group of signals.
s_axi_araddr I C_ADDR_WIDTH Read Address. The read address bus gives the initial address of a read burst transaction. Only the start address of the burst is provided and the control signals that are issued alongside the address detail how the address is calculated for the remaining transfers in the burst.
s_axi_arlen I 8 Burst Length. The burst length gives the exact number of transfers in a burst. This information determines the number of data transfers associated with the address.
s_axi_arsize I 3 Burst Size. This signal indicates the size of each transfer in the burst.
s_axi_arburst I 2 Burst Type. The burst type, coupled with the size information, details how the address for each transfer within the burst is calculated.
s_axi_arlock I 2 Lock Type. This signal provides additional information about the atomic characteristics of the transfer.
s_axi_arcache I 4 Cache Type. This signal provides additional information about the cache-able characteristics of the transfer.
s_axi_arprot I 3 Protection Type. This signal provides protection unit information for the transaction.
s_axi_arqos I 4 Quality of Service (QoS). Sent on the read address channel for each read transaction.
s_axi_arregion I 4 Region Identifier. Sent on the read address channel for each read transaction.
s_axi_aruser I C_ARUSER_WIDTH Read Address Channel User
s_axi_arvalid I 1 Read Address Valid. When High, indicates that the read address and control information is valid and will remain stable until the address acknowledge signal, arready, is High.
s_axi_arready O 1 Read Address Ready. Indicates that the slave is ready to accept an address and associated control signals.
AXI4-Lite - MM Slave Interface (Read Data Channel)
s_axi_rid O C_ID_WIDTH Read ID Tag. ID tag of the read data group of signals. The RID value is generated by the slave and must match the ARID value of the read transaction to which it is responding.
s_axi_rdata O C_DATA_WIDTH Read Data. Can be 8, 16, 32, 64, 128, 256, or 512 bits wide.
s_axi_rresp O 2 Read Response. Indicates the status of the read transfer. The allowable responses are OKAY, EXOKAY, SLVERR, and DECERR.
s_axi_rlast O 1 Read Last. Indicates the last transfer in a read burst.
s_axi_ruser O C_RUSER_WIDTH Read Data Channel User
s_axi_rvalid O 1 Read Valid. Indicates that the required read data is available and the read transfer can complete.
s_axi_rready I 1 Read Ready. Indicates that the master can accept the read data and response information.
AXI4-Lite - MM Master Interface (Write Address Channel)
m_axi_awid O C_ID_WIDTH Write Address ID. Identification tag for the write address group of signals.
m_axi_awaddr O C_ADDR_WIDTH+1 Write Address. The write address bus gives the address of the first transfer in a write burst transaction. The associated control signals are used to determine the addresses of the remaining transfers in the burst.
m_axi_awlen O 8 Burst Length. The burst length gives the exact number of transfers in a burst. This information determines the number of data transfers associated with the address.
m_axi_awsize O 3 Burst Size. Indicates the size of each transfer in the burst. Byte lane strobes indicate exactly which byte lanes to update.
m_axi_awburst O 2 Burst Type. The burst type, coupled with the size information, details how the address for each transfer within the burst is calculated.
m_axi_awlock O 2 Lock Type. This signal provides additional information about the atomic characteristics of the transfer.
m_axi_awcache O 4 Cache Type. Indicates the buffer-able, cache-able, write-through, write-back, and allocate attributes of the transaction.
m_axi_awprot O 3 Protection Type. Indicates the normal, privileged, or secure protection level of the transaction and whether the transaction is a data access or an instruction access.
m_axi_awqos O 4 Quality of Service (QoS). Sent on the write address channel for each write transaction.
m_axi_awregion O 4 Region Identifier. Sent on the write address channel for each write transaction.
m_axi_awuser O C_AWUSER_WIDTH Write Address Channel User
m_axi_awvalid O 1 Write Address Valid. Indicates that valid write address and control information are available.
m_axi_awready I 1 Write Address Ready. Indicates that the slave is ready to accept an address and associated control signals.
AXI4-Lite - MM Slave Interface (Write Data Channel)
m_axi_wdata O 2*C_DATA_WIDTH Write Data. The write data bus can be 8, 16, 32, 64, 128, 256, or 512 bits wide.
m_axi_wstrb O 2*C_DATA_WIDTH/8 Write Strobes. Indicates which byte lanes to update in memory. There is one write strobe for each eight bits of the write data bus.
m_axi_wlast O 1 Write Last. Indicates the last transfer in a write burst.
m_axi_wuser O C_WUSER_WIDTH Write Data Channel User
m_axi_wvalid O 1 Write Valid. Indicates that valid write data and strobes are available.
m_axi_wready I 1 Write Ready. Indicates that the slave can accept the write data.
AXI4-Lite - MM Slave Interface (Write Response Channel)
m_axi_bid I C_ID_WIDTH Response ID. The identification tag of the write response. The BID value must match the AWID value of the write transaction to which the slave is responding.
m_axi_bresp I 2 Write Response. Indicates the status of the write transaction. The allowable responses are OKAY, EXOKAY, SLVERR, and DECERR.
m_axi_buser I C_BUSER_WIDTH Write Response Channel User
m_axi_bvalid I 1 Write Response Valid. Indicates that a valid write response is available.
m_axi_bready O 1 Response Ready. Indicates that the master can accept the response information.
AXI4-Lite - MM Slave Interface (Read Address Channel)
m_axi_arid O C_ID_WIDTH Read Address ID. This signal is the identification tag for the read address group of signals.
m_axi_araddr O C_ADDR_WIDTH+1 Read Address. The read address bus gives the initial address of a read burst transaction. Only the start address of the burst is provided and the control signals that are issued alongside the address detail how the address is calculated for the remaining transfers in the burst.
m_axi_arlen O 8 Burst Length. The burst length gives the exact number of transfers in a burst. This information determines the number of data transfers associated with the address.
m_axi_arsize O 3 Burst Size. This signal indicates the size of each transfer in the burst.
m_axi_arburst O 2 Burst Type. The burst type, coupled with the size information, details how the address for each transfer within the burst is calculated.
m_axi_arlock O 2 Lock Type. This signal provides additional information about the atomic characteristics of the transfer.
m_axi_arcache O 4 Cache Type. This signal provides additional information about the cache-able characteristics of the transfer.
m_axi_arprot O 3 Protection Type. This signal provides protection unit information for the transaction.
m_axi_arqos O 4 Quality of Service (QoS). Sent on the read address channel for each read transaction.
m_axi_arregion O 4 Region Identifier. Sent on the read address channel for each read transaction.
m_axi_aruser O C_ARUSER_WIDTH Read Address Channel User
m_axi_arvalid O 1 Read Address Valid. When High, indicates that the read address and control information is valid and will remain stable until the address acknowledge signal, arready, is High.
m_axi_arready I 1 Read Address Ready. Indicates that the slave is ready to accept an address and associated control signals.
AXI4-Lite - MM Slave Interface (Read Data Channel)
m_axi_rid I C_ID_WIDTH Read ID Tag. ID tag of the read data group of signals. The RID value is generated by the slave and must match the ARID value of the read transaction to which it is responding.
m_axi_rdata I 2*C_DATA_WIDTH Read Data. Can be 8, 16, 32, 64, 128, 256, or 512 bits wide.
m_axi_rresp I 2 Read Response. Indicates the status of the read transfer. The allowable responses are OKAY, EXOKAY, SLVERR, and DECERR.
m_axi_rlast I 1 Read Last. Indicates the last transfer in a read burst.
m_axi_ruser I C_RUSER_WIDTH Read Data Channel User
m_axi_rvalid I 1 Read Valid. Indicates that the required read data is available and the read transfer can complete.
m_axi_rready O 1 Read Ready. Indicates that the master can accept the read data and response information.
Error Inject Signals
inject_sbiterr I 1 Inject single-bit error
inject_dbiterr I 1 Inject double-bit error
ECC Signals
dbit_err O 1 Indicates that a double-bit ECC error is detected in one or more decoders. Enabled when the sbit error read response is disabled.
sbit_err O 1 Indicates that a single-bit ECC error is detected in one or more decoders. Enabled when the sbit error read response is disabled.
Interrupts
ecc_interrupt O 1 ECC Interrupt. Indicates that a single-/double-bit error occurred on the read data path.