The Soft ECC Proxy IP core operates on a single clock (s_aclk), and all input and output interface signals of the AXI4-Lite and AXI4 master/slave interfaces are synchronized with
this clock.
The Soft ECC Proxy IP core operates on a single clock (s_aclk), and all input and output interface signals of the AXI4-Lite and AXI4 master/slave interfaces are synchronized with
this clock.