The ECC Decoder generates error correction syndrome bits for the input data and
check bits. The Hamming/HSIAO algorithm is used to generate syndrome bits inside the ECC Decoder.
These syndrome bits are used to correct any single-bit errors, or to detect (but not correct) any
double-bit errors in the input data. The single-bit error corrected data, along with the ecc_sbit_err status or the uncorrected data with ecc_dbit_err status, are provided as an output of the ECC Decoder function. For
details on the Hamming/Hsiao algorithm, see ECC LogiCORE IP Product
Guide (PG092).
The following is the block diagram of the ECC Decoder:
If no errors are detected, the input data is forwarded at the output, and both
ecc_sbit_err and ecc_dbit_err
status outputs are kept deasserted.
The OR operation of the error signals (ecc_sbit/dbit_err) is connected to the Soft ECC Proxy output ecc_interrupt.
When the sbit error slave response is disabled, the ecc_sbit_err and
ecc_dbit_err ports are available as sbit_err and
dbit_err respectively as the IP output ports.