Protocol Description - 1.1 English

This section describes the operation of the Soft ECC Proxy IP core.

Figure 1. Core Write Ports

Figure 2. Core Read Ports

The Soft ECC Proxy uses the industry standard AMBA AXI4 Protocol Specification.

AXI Register Slice: The handshake mechanism from slave AXI to master AXI is implemented with register slice for each channel.
Address Converter: The ECC value is calculated for every byte of input data separately and placed along with data bits. Each data byte concatenated with its calculated check bits (8 bits) (check bits are in MSB) and become 16 bits. Thus, N bytes of data becomes 2N bytes after encoding. The AXI4 address is byte addressable. The address value and address width can be converted to handle the doubling of data width after encoding. For example, address value 0x40 on the slave AXI interface converts to 0x80 on the master AXI interface for the same data byte.
Error Injection: The Soft ECC Proxy IP supports error injection. It can be enabled using the C_EN_ERROR_INJECT parameter. When this feature is enabled, a single/double-bit error is injected onto every byte of write data after encoding if the corresponding input signal (inject_sbiterr or dbiterr) is High. If both the input signals are High, the double-bit error is injected.
Note: One single-bit error is injected for every 16 bits of data after encoding. One double-bit error is injected for every 16 bits of data after encoding (one on actual data byte and one on an ECC byte). The position of the error changes randomly.
Read Outstanding: The Soft ECC Proxy IP supports the read outstanding feature. It can be enabled using the C_OUTSTANDING_SUPPORT_RD parameter. This parameter ranges from 1 to 64. A value of 1 means that read outstanding is not supported. A value of greater than 1 means that read outstanding is supported, which means that a number of read transactions can be stored in the read address channel AXI register slice when the master is not ready to accept the read transactions.

The following figures detail the AXI4 write burst transaction and the AXI4 read burst transaction respectively.

Figure 3. AXI4 Write Burst Transaction

From the figure:

AW_CMD_SLAVE: Write address command signals on the slave interface other than awaddr, awsize, awvalid, and awready.
W_CMD_SLAVE: Write data interface signals on the slave interface other than wdata, wstrb, wvalid, and wready.
B_CMD_SLAVE: Write response channel signals on the slave interface other than bvalid and bready.
AW_CMD_MASTER: Write burst write address command signals on the master interface other than awaddr, awsize, awvalid, and awready; .
W_CMD_MASTER: Write data interface signals on the master interface other than wdata, wstrb, wvalid, and wready.
B_CMD_MASTER: Write response channel signals on the master interface other than bvalid and bready.

Figure 4. AXI4 Read Burst Transaction

From the figure:

AR_CMD_SLAVE: Read address command signals on the slave interface other than araddr, arsize, arvalid, and arready.
R_CMD_SLAVE: Read data interface signals on the slave interface other than rdata, rvalid, and rready.
AR_CMD_MASTER: Read address command signals on the master interface other than araddr, arsize, arvalid, and arready.
R_CMD_MASTER: Read data interface signals on the master interface other than rdata, rvalid, and rready.