The following table shows the revision history for this document.
|
Date |
Version |
Revision |
|---|---|---|
|
05/17/2022 |
3.0 |
General updates. |
|
11/18/2015 |
3.0 |
Added support for UltraScale+ families. |
|
10/28/2014 |
3.0 |
Removed internal writer note. |
|
04/02/2014 |
3.0 |
Updated core to v3.0. Removed m_apb_pclk and m_apb_presetn. |
|
12/18/2013 |
2.0 |
Added UltraScale architecture support information. |
|
10/02/2013 |
2.0 |
•Updated core to v2.0. •Added Vivado IP integrator support. •Changed signal names to lowercase. •Removed design parameter descriptions. •Added example design and test bench details. •Added Debugging appendix. |
|
07/25/2012 |
1.0 |
Initial Xilinx release. This release supports Vivado Design Suite 2012.2 and Xilinx Platform Studio. This document replaces DS788, LogiCORE IP AXI to APB Bridge Data Sheet. |