When a read request and a write request are issued simultaneously (s_axi_awvalid/s_axi_wvalid and s_axi_arvalid are asserted High) from the AXI4-Lite interface, the AXI to APB Bridge core gives priority to the read request over the write request. When both write and read requests are valid, the write request is initiated on the APB after the read is requested on the APB.