Resource Utilization - 3.0 English

AXI to APB Bridge Product Guide (PG073)

Document ID

PG073

Release Date

2022-05-17

Version

3.0 English

Because the AXI to APB Bridge core is used with other designs in the FPGA, the resource utilization and timing numbers reported in this section are estimates only.

The AXI to APB Bridge core resource utilization benchmarks for several parameter combinations, measured on 7 series FPGAs, are shown in Table: Performance and Resource Utilization Benchmarks 7 Series FPGAs.

Table 2-1: Performance and Resource Utilization Benchmarks 7 Series FPGAs
Parameter Values (other parameters at default value)			Device Resources			Performance
Number of slaves	APB Protocol	Timeout value	Slices	Slice Flip-Flops	LUTs	F_MAX (MHz)
1	APB4	64	119	364	286	200
4	APB4	64	136	370	372	200
8	APB4	64	174	386	475	200
16	APB3	64	181	402	549	200

Note: Performance and utilization numbers for UltraScale architecture-based devices and Zynq®-7000 devices are expected to be similar to those for 7 series devices.