Features - 3.0 English

AXI to APB Bridge Product Guide (PG073)

Document ID

PG073

Release Date

2022-05-17

Version

3.0 English

The Xilinx AXI to APB Bridge core is a soft IP core with these features:

•AXI interface is based on the AXI4-Lite specification

•APB interface is based on the APB3 specification, supports optional APB4 selection

•Connects as a 32-bit slave on a 32-bit AXI4-Lite interface

•Connects as a 32-bit master on a 32-bit APB3/APB4 interface

•Supports optional data phase timeout

LogiCORE IP Facts Table
Core Specifics
Supported Device Family⁽¹⁾	UltraScale™+ Families, Zynq®-7000, 7 Series, UltraScale™ Architecture
Supported User Interfaces	AXI4-Lite, APB3, APB4
Resources	See Table: Performance and Resource Utilization Benchmarks 7 Series FPGAs
Provided with Core
Design Files	VHDL
Example Design	VHDL
Test Bench	VHDL
Constraints File	N/A
Simulation Model	None
Supported S/W Driver	N/A
Tested Design Flows⁽²⁾
Design Entry	Vivado® Design Suite Vivado
Simulation	For supported simulators, see the Xilinx Design Tools: Release Notes Guide.
Synthesis	Vivado Synthesis
Support
Release Notes and Known Issues	Master Answer Records: 54439
All Vivado IP Change Logs	Master Vivado IP Change Logs: 72775
Xilinx Support web page
Notes: 1.For a complete list of supported devices, see the Vivado IP catalog. 2.For the supported versions of the tools, see the Xilinx Design Tools: Release Notes Guide.