To minimize clock startup time, a 75 MHz FPGA external master configuration clock (EMCCLK) is sourced from an onboard oscillator. It is connected directly to the dedicated (EMCCLK), on bank 65.
To minimize clock startup time, a 75 MHz FPGA external master configuration clock (EMCCLK) is sourced from an onboard oscillator. It is connected directly to the dedicated (EMCCLK), on bank 65.