FPGA Bank IO Mapping

FPGA Bank IO Mapping - UG1607

Alveo X3522PV Adaptable Accelerator Card User Guide (UG1607)

Document ID

UG1607

Release Date

2022-10-18

Revision

1.0 English

The following table provides the FPGA bank IO allocation along with additional details including assigned function and VCCO allocation. Allocation of bank type is dependent on the required function. Dedicated bank 0 is allocated for JTAG and configuration QSPI interface, and it is not detailed in the table.

Table 1. FPGA Bank Allocation
FPGA Bank	Bank Type	Function	VCCO
65	HPIO	FPGA SC UART FPGA UART DSFP28 ports 1-2 LED FPGA SC I2C Interface 1PPS IN, OUT	1.8
66 - 68	HPIO	DDR4 Controller	1.2
224 - 225	GTY	PCIe x8 to Edge Connector PCIe Lane 3-0 on bank 225 PCIe Lane 7-4 on bank 224 Upper 8 PCIe lanes of 16 are not allocated at the FGPA; the PCIe edge connector is only 8-lanes wide.	NA
231	GTY	DSFP28 Port 1 & Port2	NA