Step 1: Creating a New Project - 2022.1 English

Vivado Design Suite Tutorial: Power Analysis and Optimization (UG997)

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2022.1 English
IP integrator (IPI) is used to create the design.

On Linux, do the following.

  1. Go to the directory where the lab materials are stored:

    cd <Extract_Dir>/Versal (for Versal devices)

  2. Launch Vivado IDE: vivado

    On Windows, do the following.

  3. Launch the Vivado IDE by selecting Start > All Programs > Xilinx Design Tools > Vivado 2022.x > Vivado 2022.x (x denotes the latest version of Vivado 2022 IDE).

    As an alternative, click the Vivado 2022.x Desktop icon to start the Vivado IDE.

    The Vivado IDE Getting Started page contains links to open or create projects, and to view documentation.

  4. In the Getting Started page, click in Tcl Console to type the command.
  5. Type the following command to generate a block design (BD): source <Extract_Dir/Versal/design.tcl .
    Note: It might take a moment for the design to initialize in Vivado IDE.

  6. When the block design is generated, you can find the block design file ( in the Sources window. A top-level HDL wrapper around the block design is needed because a BD source cannot be synthesized.
  7. To generate HDL wrapper:
    1. Right-click on your block design source file ( under Design Sources drop-down.
    2. Click Create HDL Wrapper option.

    3. In the Create HDL Wrapper dialog box, select Let Vivado manage wrapper and auto-update option and click OK.

The design is now ready for synthesis.