You can find a separate UltraScale+ folder containing the UltraScale+ tutorial design files in the contents of the zip file.
The following table describes the contents of the UltraScale+™ tutorial design files:
| Files | Description |
|---|---|
| /src | Contains the design HDL and testbench for the simulation. |
| /src/dut_fpga.v | Top module for the design. |
|
/src/dut.v /src/Cascade_bram.v /src/Noncascade_bram.v /src/bram_top_cascade.v /src/bram_top_noncascade.v /src/bram_tdp_cas.v /src/bram_tdp_noncas.v |
Other design blocks. |
| dut_fpga_zcu102.xdc | Contains clocking and timing constraints for the design. |
| /src/testbench.v | Testbench for simulating the design. |