Vivado IDE allows you to specify the input data to the Report Power tool to enhance the accuracy of the power analysis.
In Vivado IDE, you can configure thermal, environmental, and power supply options to mimic the board level settings as closely as possible. For information on setting these options, see the Vivado Design Suite User Guide: Power Analysis and Optimization (UG907).
- In the main menu bar, select .
- Examine the Environment tab in the Report Power dialog box.
- In the Environment
tab, set Process to maximum for worst case power analysis.
Examine the Power
Supply tab.Important: By default, Vivado Report Power uses nominal values for voltage supply sources. Voltage is a large factor contributing to both static and dynamic power. For the most accurate analysis, ensure that actual voltage values are entered for each supply. Similarly, ensure that the temperature and other environmental factors match the actual operating conditions.
- In the Switching
tab, expand Constrained
Clocks and examine the constrained clocks in the
design.Important: Make sure all the relevant clocks in the design are constrained. All the design clocks must be defined using
create_clock
orcreate_generated_clock
XDC constraints, so that Report Power recognizes the clocks.Make sure that the Default toggle rate is set to 12.5% and Default Static Probability is set to 0.5. This is applied to primary input ports (non-clock) and black box outputs.
- In the Output tab of the Report Power dialog box, specify Export to file as power_1.pwr.
- Specify the Output XPE file as power_1.xpe. After creating this file, when Report Power runs, you can import the file and its results into the Xilinx Power Estimator. For information on importing the file into the Xilinx Power Estimator, see the Xilinx Power Estimator User Guide (UG440).
- Specify the RPX file by setting Interactive report
file as
power_1.rpx to write the results of
the Report Power
command. The saved RPX file can be reloaded using the command to provide interaction or cross-probing with the open
design.