Generating a SAIF File using Questa Advanced Simulator - 2022.1 English - UG997

Vivado Design Suite Tutorial: Power Analysis and Optimization (UG997)
Document ID
UG997
Release Date
2022-06-15
Version
2022.1 English

The following steps will take you through the process of SAIF file creation, running timing simulation, and estimating power using SAIF data using the Questa Advanced Simulator.

Important: Make sure that the Vivado Design Suite knows where to pick up the Questa Advanced Simulator tool. You can either:

Manually set the path to ModelSim/Questa Advanced Simulator using the $PATH environment variable

or

In Vivado IDE, click Tools > Settings > Tool Settings, and define the path to the Questa Advanced Simulator on the 3rd Party Tools page.

Make sure the Default Compiled Library Paths points to a valid location for the compiled Xilinx simulation libraries.

To create new compiled libraries:

  1. In the 3rd Party Simulators page, specify the compiled library path for Questa Advanced Simulator in the Questa field under Default Compiled Library Paths. Enter the Compiled library location specified during the compiled library generation. It should point to the compile_simlib directory.
  2. Click OK to define the path and generate compiled libraries.