DPU Naming - 1.2 English

Vitis AI User Guide (UG1414)

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1.2 English

Starting from Vitis AI 1.2, a new DPU naming is used to better differentiate various DPUs served for different purposes. The old DPUv1/v2/v3 naming is deprecated.

The new DPU naming convention is shown in the following illustration:
Figure 1. DPU Naming Convention

DPU Naming Example

To better understand the mapping of the old DPU names into this naming, see the following table:

Table 1. DPU Naming Examples
Example DPUv1 DPUv2 DPUv3e DPUv3me DPUv3int8 XRNN
Application (C, R, B,F) C C C C C R
Hardware Platform (AD, AH, VD, VH, ZD) AD ZD AH AH AD AH
Quantization Method (X, F, I) X X X X F R
Quantization Bitwidth (4, 8, 16, M) 8 8 8 8 8 16
Design Target (G, H, L, P,C) G G H L H L
Major 3 1 1 1 1 1
Minor 0 4 0 0 0 0
Patch 0 1 0 0 0 0
DPU Name DPUCADX8G-3.0.0 DPUCZDX8G-1.4.1 DPUCAHX8H-1.0.0 DPUCAHX8L-1.0.0 DPUCADF8H-1.0.0 DPURAHR16L-1.0.0
  1. For Application, C-CNN, R-RNN
  2. For Hardware platform, AD-Alveo DDR; AH-Alveo HBM; VD-Versal DDR with AIE and PL; ZD-Zynq DDR
  3. For Quantization method, X-Decent; F- Float threshold; I-Integer threshold; R-RNN
  4. For Quantization bandwidth, 4-4 bit; 8-8 bit; 16-16 bit; M- Mixed precision
  5. For Design target, G-General purpose; H-High throughput; L-Low latency; C-Cost optimized