Core Specifics |
Supported Device Family |
Alveo™
U280/U55C and U50/U50LV Data Center
accelerator cards
|
Supported User Interfaces |
AXI4-Lite CSR
Interface |
Resources |
DPU Configuration
|
Provided with
Core
|
Design Files |
Encrypted RTL |
Example Design |
Verilog |
Test Bench |
Not Provided |
Constraints File |
Xilinx Constraints File |
Simulation Model |
Not Provided |
Supported S/W Driver
1
|
Xilinx®
Runtime (XRT) |
Tested Design Flows
2
|
Design Entry |
Vitis™
unified software platform |
Simulation |
N/A |
Synthesis |
Vivado®
Synthesis |
Support |
Xilinx
Support web page
|
-
Vitis™
AI development flow.
- For the supported versions of the tools, see
the Linux OS and driver support information are available from the
Vitis
Unified Software Platform Documentation: Application
Acceleration Development (UG1393).
|