Configuring the HBM - 1.1 English

DPUCAHX8H for Convolutional Neural Networks (PG367)
Document ID
PG367
Release Date
2022-04-14
Version
1.1 English
The Alveo™ U50, U50LV, U55C, and U280 cards support HBM. This section describes how to customize the HBM IP to meet DPU requirements and improve performance.

Although each AXI port connected to the HBM controller (HMSS) can access all the DDR memory banks within the HBM, care is needed to minimize the cross-bank traffic inside the HBM switch. This is done by using the HBM AXI port associated with each HBM memory bank, or immediate neighbor bank. To get better access performance, each feature map AXI port must be constrained at a DDR memory bank to avoid latency caused by inefficient horizontal access.

To configure the HBM, follow these steps:

  1. Add the sp constraints to the cons.ini file. In this example, the connectivity of each AXI port covers full HBM-range access.
    [connectivity]
nk=DPUCAHX8H_5ENGINE:1:dpu_0
nk=DPUCAHX8H_5ENGINE:1:dpu_1
sp=dpu_0.DPU_AXI_0:HBM[00:31]
sp=dpu_0.DPU_AXI_1:HBM[00:31]
sp=dpu_0.DPU_AXI_4:HBM[00:31]
sp=dpu_1.DPU_AXI_0:HBM[00:31]
sp=dpu_1.DPU_AXI_1:HBM[00:31]
sp=dpu_1.DPU_AXI_4:HBM[00:31]
sp=dpu_0.DPU_AXI_I0:HBM[00:31]
sp=dpu_1.DPU_AXI_I0:HBM[00:31]
sp=dpu_0.DPU_AXI_2:HBM[00:31]
sp=dpu_0.DPU_AXI_3:HBM[00:31]
sp=dpu_1.DPU_AXI_2:HBM[00:31]
sp=dpu_1.DPU_AXI_3:HBM[00:31]
sp=dpu_0.DPU_AXI_W0:HBM[00:31]
sp=dpu_0.DPU_AXI_W1:HBM[00:31]
sp=dpu_1.DPU_AXI_W0:HBM[00:31]
sp=dpu_1.DPU_AXI_W1:HBM[00:31]
  2. Use the --config "cons.ini" command to the v++ command.
  3. Put the following code at sys_link_post.tcl for one core:
    hbm_memory_subsystem::force_host_port 28 1 [get_bd_cells hmss_0]
hbm_memory_subsystem::force_kernel_port [get_bd_intf_pins /dpu_0/DPU_AXI_0] 0 1 [get_bd_cells hmss_0]
hbm_memory_subsystem::force_kernel_port [get_bd_intf_pins /dpu_0/DPU_AXI_1] 1 1 [get_bd_cells hmss_0]
hbm_memory_subsystem::force_kernel_port [get_bd_intf_pins /dpu_0/DPU_AXI_4] 2 1 [get_bd_cells hmss_0]
hbm_memory_subsystem::force_kernel_port [get_bd_intf_pins /dpu_1/DPU_AXI_0] 3 1 [get_bd_cells hmss_0]
hbm_memory_subsystem::force_kernel_port [get_bd_intf_pins /dpu_1/DPU_AXI_1] 4 1 [get_bd_cells hmss_0]
hbm_memory_subsystem::force_kernel_port [get_bd_intf_pins /dpu_1/DPU_AXI_4] 5 1 [get_bd_cells hmss_0]
hbm_memory_subsystem::force_kernel_port [get_bd_intf_pins /dpu_0/DPU_AXI_I0] 6 1 [get_bd_cells hmss_0]
hbm_memory_subsystem::force_kernel_port [get_bd_intf_pins /dpu_1/DPU_AXI_I0] 7 1 [get_bd_cells hmss_0]
hbm_memory_subsystem::force_kernel_port [get_bd_intf_pins /dpu_0/DPU_AXI_2] 16 1 [get_bd_cells hmss_0]
hbm_memory_subsystem::force_kernel_port [get_bd_intf_pins /dpu_0/DPU_AXI_3] 17 1 [get_bd_cells hmss_0]
hbm_memory_subsystem::force_kernel_port [get_bd_intf_pins /dpu_1/DPU_AXI_2] 18 1 [get_bd_cells hmss_0]
hbm_memory_subsystem::force_kernel_port [get_bd_intf_pins /dpu_1/DPU_AXI_3] 19 1 [get_bd_cells hmss_0]
hbm_memory_subsystem::force_kernel_port [get_bd_intf_pins /dpu_0/DPU_AXI_W0] 20 1 [get_bd_cells hmss_0]
hbm_memory_subsystem::force_kernel_port [get_bd_intf_pins /dpu_0/DPU_AXI_W1] 21 1 [get_bd_cells hmss_0]
hbm_memory_subsystem::force_kernel_port [get_bd_intf_pins /dpu_1/DPU_AXI_W0] 22 1 [get_bd_cells hmss_0]
hbm_memory_subsystem::force_kernel_port [get_bd_intf_pins /dpu_1/DPU_AXI_W1] 23 1 [get_bd_cells hmss_0]
  4. Add the following lines to the cons.ini file.
    [advanced]
param=compiler.userPostSysLinkTcl=*/sys_link_post.tcl