Run the following command to generate the bitstream:
v++ -t hw --platform $platform_name --temp_dir $direction_name -l --config "cons.ini" -o dpu.xclbin DPUCAHX8H_*ENGINE.xo
If more than one xo is used, add the xo file names in the command as shown in the following example for implementing the 4ENGINE at SLR0+ 5 ENGINE at SLR1 on the Alveo U50LV card:
v++ -t hw --platform xilinx_u50lv_gen3x4_xdma_2_202010_1 --save-temps -- temp_dir imp_dir -l --config "deephi.ini" -o dpu.xclbin DPUCAHX8H_4ENGINE.xo DPUCAHX8H_5ENGINE.xo