- Supports one AXI slave interface for accessing configuration and status registers.
- Supports one AXI master interface for loading instructions.
- Supports two AXI master interfaces for loading model parameters.
- Supports one to five AXI master interfaces for accessing input/output/intermediate feature map stored in the HBM.
- Supports all AXI master interfaces with 256-bit width.
- DPU functionality includes the following:
- Configurable number of processing engines (PE)
- Convolution and deconvolution
- Depthwise convolution
- Maximum and average pooling
- ReLU, ReLU6, and Leaky ReLU
- Data split
- Concat
- Elementwise-sum
- Dilation
- Data reorganization
- Fully connected layer
- Batch normalization