Core Overview - 1.0 English

DPUCAHX8H for Convolutional Neural Networks (PG367)

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1.0 English

The Xilinx® DPUCAHX8H is a programmable DPU core optimized for convolutional neural networks, mainly for high throughput applications. The core includes a high-performance scheduler module, a hybrid computing array module, an instruction fetch module, and a frame buffer module. It uses a specialized instruction set that allows efficient implementation of many convolutional neural networks. Some examples of convolutional neural networks which have been deployed include VGG, ResNet, GoogLeNet, YOLO, SSD, FPN, and many others.

The DPUCAHX8H is implemented in the programmable logic (PL) of the Alveo™ U280 and U50/U50LV Data Center accelerator cards.

The following figure shows the top-level block diagram of the DPUCAHX8H:

Figure 1. DPU Top-Level Block Diagram