IP Facts - 1.0 English

DPUCAHX8H for Convolutional Neural Networks (PG367)

Document ID
Release Date
1.0 English
LogiCORE™ IP Facts Table
Core Specifics
Supported Device Family Alveo™ U280 and U50/U50LV Data Center accelerator cards
Supported User Interfaces AXI4-Lite CSR Interface
Resources DPU Configuration
Provided with Core
Design Files Encrypted RTL
Example Design Verilog
Test Bench Not Provided
Constraints File Xilinx Constraints File
Simulation Model Not Provided
Supported S/W Driver 1 Xilinx® Runtime (XRT)
Tested Design Flows 2
Design Entry Vitis™ unified software platform
Simulation N/A
Synthesis Vivado® Synthesis
Xilinx Support web page
  1. Vitis™ AI development flow.
  2. For the supported versions of the tools, see the Linux OS and driver support information are available from the Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393).