DPU Control Registers - 1.0 English

DPUCAHX8H for Convolutional Neural Networks (PG367)

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The DPU control registers are used to start a DPU core, waiting for task finish and then clear DPU status. The details of control registers are shown in the following table.
Table 1. DPU Control Registers
Register Address Offset Width Type Description
reg_ap_control 0x000 32 r/w
  • Bit 0: ap_start (read/write/clear on handshake)
  • Bit 1: ap_done (read/clear on read)
  • Bit 2: ap_idle (read)
  • Others: reserved
Global interrupt enable register (GIER) 0x004 32 r/w
  • Bit 0: global interrupt enable
  • Others: reserved
IP interrupt enable register (IPIER) 0x008 32 r/w
  • Bit 0: channel 0 (ap_done)
  • Others: reserved
IP interrupt status register (IPISR) 0x00c 32 r/w
  • Bit 0: channel 0 (ap_done) (read/toggle on write)
  • Others: reserved
reg_dpu_start 0x010 32 r/w
  • Bit [0]: enable DPU to start
reg_finish_clr 0x018 32 r/w
  • Bit [0]: clear reg_finish_sts
reg_finish_sts 0x080 32 r
  • Bit [0]: indicate DPU has finished.

The DPU finish signal is also output as DPU interrupt to trigger XDMA or custom logic.

The DPU finish is a level and asynchronous signal.