Stream_Switch_Master_Config_South0 (AIE_CORE_MODULE) Register

Versal Adaptive SoC AI Engine Register Reference (AM015)

Document ID
AM015
Release Date
2024-04-12
Revision
1.2

Stream_Switch_Master_Config_South0 (AIE_CORE_MODULE) Register Description

Register NameStream_Switch_Master_Config_South0
Offset Address0x000003F01C
Absolute Address For calculated base addresses for each device, see Answer Record 000036195.
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionStream Switch Master Configuration South 0

Stream_Switch_Master_Config_South0 (AIE_CORE_MODULE) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Master_Enable31rwNormal read/write0x01=enable the master port
Packet_Enable30rwNormal read/write0x00=circuit; 1=packet switching mode for master port
Drop_Header 7rwNormal read/write0x01=drop header on packet
Configuration 6:0rwNormal read/write0x0circuit: [4:0]=slave port; packet: [2:0]=arbitor, [6:3]=msel_enable