AIE_CORE_MODULE Module

Versal Adaptive SoC AI Engine Register Reference (AM015)

Document ID

AM015

Release Date

2024-04-12

Revision

1.2

AIE_CORE_MODULE Module Description

Module Name	AIE_CORE_MODULE Module
Base Addresses	The register base addresses for compute modules can be found by using the following formula: Register Base Address = 0x200_0000_0000 + (<colnum> * 32 + <rownum + 1>) * 0x4_0000 Note: The first row of compute tiles is rownum 0. For the calculated addresses for each device, see Answer Record 000036195.
Description	AI Engine Core Module

Module Name

AIE_CORE_MODULE Module

Base Addresses

The register base addresses for compute modules can be found by using the following formula:

Note: The first row of compute tiles is rownum 0.

For the calculated addresses for each device, see Answer Record 000036195.

Description

AI Engine Core Module

AIE_CORE_MODULE Module Register Summary

Register Name	Offset Address	Width	Type	Reset Value	Description
Program_Memory	0x0000020000	128	rwNormal read/write	0x00000000	Program Memory (16 kbyte)
Core_R0	0x0000030000	32	rwNormal read/write	0x00000000	General purpose register
Core_R1	0x0000030010	32	rwNormal read/write	0x00000000	General purpose register
Core_R2	0x0000030020	32	rwNormal read/write	0x00000000	General purpose register
Core_R3	0x0000030030	32	rwNormal read/write	0x00000000	General purpose register
Core_R4	0x0000030040	32	rwNormal read/write	0x00000000	General purpose register
Core_R5	0x0000030050	32	rwNormal read/write	0x00000000	General purpose register
Core_R6	0x0000030060	32	rwNormal read/write	0x00000000	General purpose register
Core_R7	0x0000030070	32	rwNormal read/write	0x00000000	General purpose register
Core_R8	0x0000030080	32	rwNormal read/write	0x00000000	General purpose register
Core_R9	0x0000030090	32	rwNormal read/write	0x00000000	General purpose register
Core_R10	0x00000300A0	32	rwNormal read/write	0x00000000	General purpose register
Core_R11	0x00000300B0	32	rwNormal read/write	0x00000000	General purpose register
Core_R12	0x00000300C0	32	rwNormal read/write	0x00000000	General purpose register
Core_R13	0x00000300D0	32	rwNormal read/write	0x00000000	General purpose register
Core_R14	0x00000300E0	32	rwNormal read/write	0x00000000	General purpose register
Core_R15	0x00000300F0	32	rwNormal read/write	0x00000000	General purpose register
Core_P0	0x0000030100	20	rwNormal read/write	0x00000000	Pointer register
Core_P1	0x0000030110	20	rwNormal read/write	0x00000000	Pointer register
Core_P2	0x0000030120	20	rwNormal read/write	0x00000000	Pointer register
Core_P3	0x0000030130	20	rwNormal read/write	0x00000000	Pointer register
Core_P4	0x0000030140	20	rwNormal read/write	0x00000000	Pointer register
Core_P5	0x0000030150	20	rwNormal read/write	0x00000000	Pointer register
Core_P6	0x0000030160	20	rwNormal read/write	0x00000000	Pointer register
Core_P7	0x0000030170	20	rwNormal read/write	0x00000000	Pointer register
Core_CL0	0x0000030180	32	rwNormal read/write	0x00000000	Configuration register
Core_CH0	0x0000030190	32	rwNormal read/write	0x00000000	Configuration register
Core_CL1	0x00000301A0	32	rwNormal read/write	0x00000000	Configuration register
Core_CH1	0x00000301B0	32	rwNormal read/write	0x00000000	Configuration register
Core_CL2	0x00000301C0	32	rwNormal read/write	0x00000000	Configuration register
Core_CH2	0x00000301D0	32	rwNormal read/write	0x00000000	Configuration register
Core_CL3	0x00000301E0	32	rwNormal read/write	0x00000000	Configuration register
Core_CH3	0x00000301F0	32	rwNormal read/write	0x00000000	Configuration register
Core_CL4	0x0000030200	32	rwNormal read/write	0x00000000	Configuration register
Core_CH4	0x0000030210	32	rwNormal read/write	0x00000000	Configuration register
Core_CL5	0x0000030220	32	rwNormal read/write	0x00000000	Configuration register
Core_CH5	0x0000030230	32	rwNormal read/write	0x00000000	Configuration register
Core_CL6	0x0000030240	32	rwNormal read/write	0x00000000	Configuration register
Core_CH6	0x0000030250	32	rwNormal read/write	0x00000000	Configuration register
Core_CL7	0x0000030260	32	rwNormal read/write	0x00000000	Configuration register
Core_CH7	0x0000030270	32	rwNormal read/write	0x00000000	Configuration register
Core_PC	0x0000030280	20	rwNormal read/write	0x00000000	Program Counter
Core_FC	0x0000030290	20	rwNormal read/write	0x00000000	Fetch Counter
Core_SP	0x00000302A0	20	rwNormal read/write	0x00000000	Stack Pointer
Core_LR	0x00000302B0	20	rwNormal read/write	0x00000000	Link Register
Core_M0	0x00000302C0	20	rwNormal read/write	0x00000000	Modifier register
Core_M1	0x00000302D0	20	rwNormal read/write	0x00000000	Modifier register
Core_M2	0x00000302E0	20	rwNormal read/write	0x00000000	Modifier register
Core_M3	0x00000302F0	20	rwNormal read/write	0x00000000	Modifier register
Core_M4	0x0000030300	20	rwNormal read/write	0x00000000	Modifier register
Core_M5	0x0000030310	20	rwNormal read/write	0x00000000	Modifier register
Core_M6	0x0000030320	20	rwNormal read/write	0x00000000	Modifier register
Core_M7	0x0000030330	20	rwNormal read/write	0x00000000	Modifier register
Core_CB0	0x0000030340	20	rwNormal read/write	0x00000000	Circular buffer start address
Core_CB1	0x0000030350	20	rwNormal read/write	0x00000000	Circular buffer start address
Core_CB2	0x0000030360	20	rwNormal read/write	0x00000000	Circular buffer start address
Core_CB3	0x0000030370	20	rwNormal read/write	0x00000000	Circular buffer start address
Core_CB4	0x0000030380	20	rwNormal read/write	0x00000000	Circular buffer start address
Core_CB5	0x0000030390	20	rwNormal read/write	0x00000000	Circular buffer start address
Core_CB6	0x00000303A0	20	rwNormal read/write	0x00000000	Circular buffer start address
Core_CB7	0x00000303B0	20	rwNormal read/write	0x00000000	Circular buffer start address
Core_CS0	0x00000303C0	20	rwNormal read/write	0x00000000	Circular buffer size
Core_CS1	0x00000303D0	20	rwNormal read/write	0x00000000	Circular buffer size
Core_CS2	0x00000303E0	20	rwNormal read/write	0x00000000	Circular buffer size
Core_CS3	0x00000303F0	20	rwNormal read/write	0x00000000	Circular buffer size
Core_CS4	0x0000030400	20	rwNormal read/write	0x00000000	Circular buffer size
Core_CS5	0x0000030410	20	rwNormal read/write	0x00000000	Circular buffer size
Core_CS6	0x0000030420	20	rwNormal read/write	0x00000000	Circular buffer size
Core_CS7	0x0000030430	20	rwNormal read/write	0x00000000	Circular buffer size
Core_MD0	0x0000030440	32	rwNormal read/write	0x00000000	Mode control register
Core_MD1	0x0000030450	32	rwNormal read/write	0x00000000	Mode control register
Core_MC0	0x0000030460	32	rwNormal read/write	0x00000000	Status register
Core_MC1	0x0000030470	32	rwNormal read/write	0x00000000	Status register
Core_S0	0x0000030480	8	rwNormal read/write	0x00000000	Shift Control
Core_S1	0x0000030490	8	rwNormal read/write	0x00000000	Shift Control
Core_S2	0x00000304A0	8	rwNormal read/write	0x00000000	Shift Control
Core_S3	0x00000304B0	8	rwNormal read/write	0x00000000	Shift Control
Core_S4	0x00000304C0	8	rwNormal read/write	0x00000000	Shift Control
Core_S5	0x00000304D0	8	rwNormal read/write	0x00000000	Shift Control
Core_S6	0x00000304E0	8	rwNormal read/write	0x00000000	Shift Control
Core_S7	0x00000304F0	8	rwNormal read/write	0x00000000	Shift Control
Core_LS	0x0000030500	20	rwNormal read/write	0x00000000	Loop Start register
Core_LE	0x0000030510	20	rwNormal read/write	0x000FFFFF	Loop Exit register
Core_LC	0x0000030520	32	rwNormal read/write	0x00000000	Loop count register
Core_VRL0	0x0000030530	128	rwNormal read/write	0x00000000	VRL0 register
Core_VRH0	0x0000030540	128	rwNormal read/write	0x00000000	VRH0 register
Core_VRL1	0x0000030550	128	rwNormal read/write	0x00000000	VRL1 register
Core_VRH1	0x0000030560	128	rwNormal read/write	0x00000000	VRH1 register
Core_VRL2	0x0000030570	128	rwNormal read/write	0x00000000	VRL2 register
Core_VRH2	0x0000030580	128	rwNormal read/write	0x00000000	VRH2 register
Core_VRL3	0x0000030590	128	rwNormal read/write	0x00000000	VRL3 register
Core_VRH3	0x00000305A0	128	rwNormal read/write	0x00000000	VRH3 register
Core_VCL0	0x00000305B0	128	rwNormal read/write	0x00000000	VCL0 register
Core_VCH0	0x00000305C0	128	rwNormal read/write	0x00000000	VCH0 register
Core_VCL1	0x00000305D0	128	rwNormal read/write	0x00000000	VCL1 register
Core_VCH1	0x00000305E0	128	rwNormal read/write	0x00000000	VCH1 register
Core_VDL0	0x00000305F0	128	rwNormal read/write	0x00000000	VDL0 register
Core_VDH0	0x0000030600	128	rwNormal read/write	0x00000000	VDH0 register
Core_VDL1	0x0000030610	128	rwNormal read/write	0x00000000	VDL1 register
Core_VDH1	0x0000030620	128	rwNormal read/write	0x00000000	VDH1 register
Core_AML0_Part1	0x0000030630	128	rwNormal read/write	0x00000000	AML0 register (part1)
Core_AML0_Part2	0x0000030640	128	rwNormal read/write	0x00000000	AML0 register (part2)
Core_AML0_Part3	0x0000030650	128	rwNormal read/write	0x00000000	AML0 register (part3)
Core_AMH0_Part1	0x0000030660	128	rwNormal read/write	0x00000000	AMH0 register (part1)
Core_AMH0_Part2	0x0000030670	128	rwNormal read/write	0x00000000	AMH0 register (part2)
Core_AMH0_Part3	0x0000030680	128	rwNormal read/write	0x00000000	AMH0 register (part3)
Core_AML1_Part1	0x0000030690	128	rwNormal read/write	0x00000000	AML1 register (part1)
Core_AML1_Part2	0x00000306A0	128	rwNormal read/write	0x00000000	AML1 register (part2)
Core_AML1_Part3	0x00000306B0	128	rwNormal read/write	0x00000000	AML1 register (part3)
Core_AMH1_Part1	0x00000306C0	128	rwNormal read/write	0x00000000	AMH1 register (part1)
Core_AMH1_Part2	0x00000306D0	128	rwNormal read/write	0x00000000	AMH1 register (part2)
Core_AMH1_Part3	0x00000306E0	128	rwNormal read/write	0x00000000	AMH1 register (part3)
Core_AML2_Part1	0x00000306F0	128	rwNormal read/write	0x00000000	AML1 register (part1)
Core_AML2_Part2	0x0000030700	128	rwNormal read/write	0x00000000	AML1 register (part2)
Core_AML2_Part3	0x0000030710	128	rwNormal read/write	0x00000000	AML1 register (part3)
Core_AMH2_Part1	0x0000030720	128	rwNormal read/write	0x00000000	AMH1 register (part1)
Core_AMH2_Part2	0x0000030730	128	rwNormal read/write	0x00000000	AMH1 register (part2)
Core_AMH2_Part3	0x0000030740	128	rwNormal read/write	0x00000000	AMH1 register (part3)
Core_AML3_Part1	0x0000030750	128	rwNormal read/write	0x00000000	AML1 register (part1)
Core_AML3_Part2	0x0000030760	128	rwNormal read/write	0x00000000	AML1 register (part2)
Core_AML3_Part3	0x0000030770	128	rwNormal read/write	0x00000000	AML1 register (part3)
Core_AMH3_Part1	0x0000030780	128	rwNormal read/write	0x00000000	AMH1 register (part1)
Core_AMH3_Part2	0x0000030790	128	rwNormal read/write	0x00000000	AMH1 register (part2)
Core_AMH3_Part3	0x00000307A0	128	rwNormal read/write	0x00000000	AMH1 register (part3)
Performance_Ctrl0	0x0000031000	32	rwNormal read/write	0x00000000	Performance Counters 1-0 Start and Stop Event
Performance_Ctrl1	0x0000031004	32	rwNormal read/write	0x00000000	Performance Counters 3-2 Start and Stop Event
Performance_Ctrl2	0x0000031008	32	rwNormal read/write	0x00000000	Performance Counters Reset Events
Performance_Counter0	0x0000031020	32	rwNormal read/write	0x00000000	Performance Counter0
Performance_Counter1	0x0000031024	32	rwNormal read/write	0x00000000	Performance Counter1
Performance_Counter2	0x0000031028	32	rwNormal read/write	0x00000000	Performance Counter2
Performance_Counter3	0x000003102C	32	rwNormal read/write	0x00000000	Performance Counter3
Performance_Counter0_Event_Value	0x0000031080	32	rwNormal read/write	0x00000000	Performance Counter0 Event Value.
Performance_Counter1_Event_Value	0x0000031084	32	rwNormal read/write	0x00000000	Performance Counter1 Event Value. When the Performance Counter1 reach this value, an event will be generated
Performance_Counter2_Event_Value	0x0000031088	32	rwNormal read/write	0x00000000	Performance Counter2 Event Value. When the Performance Counter2 reach this value, an event will be generated
Performance_Counter3_Event_Value	0x000003108C	32	rwNormal read/write	0x00000000	Performance Counter3 Event Value. When the Performance Counter3 reach this value, an event will be generated
Core_Control	0x0000032000	32	rwNormal read/write	0x00000002	Control of the AI Engine
Core_Status	0x0000032004	32	roRead-only	0x00000002	The status of the AI Engine
Enable_Events	0x0000032008	32	mixedMixed types. See bit-field details.	0x00000000	Set reset event trigger
Reset_Event	0x000003200C	32	rwNormal read/write	0x00000000	Set reset event trigger
Debug_Control0	0x0000032010	32	rwNormal read/write	0x00000000	Debug control of manual debug stall and single step count
Debug_Control1	0x0000032014	32	rwNormal read/write	0x00000000	Debug Halt Event Control
Debug_Control2	0x0000032018	32	rwNormal read/write	0x00000000	Debug Halt Control
Debug_Status	0x000003201C	32	roRead-only	0x00000000	Debug Status
PC_Event0	0x0000032020	32	rwNormal read/write	0x00000000	PC_Event0
PC_Event1	0x0000032024	32	rwNormal read/write	0x00000000	PC_Event1
PC_Event2	0x0000032028	32	rwNormal read/write	0x00000000	PC_Event2
PC_Event3	0x000003202C	32	rwNormal read/write	0x00000000	PC_Event3
Error_Halt_Control	0x0000032030	32	wtcReadable, write a 1 to clear	0x00000000	Error Halt Control
Error_Halt_Event	0x0000032034	32	rwNormal read/write	0x00000000	Error Halt Event
Timer_Control	0x0000034000	32	mixedMixed types. See bit-field details.	0x00000000	Control of Internal Timer
Event_Generate	0x0000034008	32	woWrite-only	0x00000000	Generate an internal event
Event_Broadcast0	0x0000034010	32	rwNormal read/write	0x00000000	Control of which Internal Event to Broadcast0
Event_Broadcast1	0x0000034014	32	rwNormal read/write	0x00000000	Control of which Internal Event to Broadcast1
Event_Broadcast2	0x0000034018	32	rwNormal read/write	0x00000000	Control of which Internal Event to Broadcast2
Event_Broadcast3	0x000003401C	32	rwNormal read/write	0x00000000	Control of which Internal Event to Broadcast3
Event_Broadcast4	0x0000034020	32	rwNormal read/write	0x00000000	Control of which Internal Event to Broadcast4
Event_Broadcast5	0x0000034024	32	rwNormal read/write	0x00000000	Control of which Internal Event to Broadcast5
Event_Broadcast6	0x0000034028	32	rwNormal read/write	0x00000000	Control of which Internal Event to Broadcast6
Event_Broadcast7	0x000003402C	32	rwNormal read/write	0x00000000	Control of which Internal Event to Broadcast7
Event_Broadcast8	0x0000034030	32	rwNormal read/write	0x00000000	Control of which Internal Event to Broadcast8
Event_Broadcast9	0x0000034034	32	rwNormal read/write	0x00000000	Control of which Internal Event to Broadcast9
Event_Broadcast10	0x0000034038	32	rwNormal read/write	0x00000000	Control of which Internal Event to Broadcast10
Event_Broadcast11	0x000003403C	32	rwNormal read/write	0x00000000	Control of which Internal Event to Broadcast11
Event_Broadcast12	0x0000034040	32	rwNormal read/write	0x00000000	Control of which Internal Event to Broadcast12
Event_Broadcast13	0x0000034044	32	rwNormal read/write	0x00000000	Control of which Internal Event to Broadcast13
Event_Broadcast14	0x0000034048	32	rwNormal read/write	0x00000000	Control of which Internal Event to Broadcast14
Event_Broadcast15	0x000003404C	32	rwNormal read/write	0x00000000	Control of which Internal Event to Broadcast15
Event_Broadcast_Block_South_Set	0x0000034050	32	woWrite-only	0x00000000	Set block of broadcast signals to South
Event_Broadcast_Block_South_Clr	0x0000034054	32	woWrite-only	0x00000000	Clear block of broadcast signals to South
Event_Broadcast_Block_South_Value	0x0000034058	32	roRead-only	0x00000000	Current value of block for broadcast signals to South
Event_Broadcast_Block_West_Set	0x0000034060	32	woWrite-only	0x00000000	Set block of broadcast signals to West
Event_Broadcast_Block_West_Clr	0x0000034064	32	woWrite-only	0x00000000	Clear block of broadcast signals to West
Event_Broadcast_Block_West_Value	0x0000034068	32	roRead-only	0x00000000	Current value of block for broadcast signals to West
Event_Broadcast_Block_North_Set	0x0000034070	32	woWrite-only	0x00000000	Set block of broadcast signals to North
Event_Broadcast_Block_North_Clr	0x0000034074	32	woWrite-only	0x00000000	Clear block of broadcast signals to North
Event_Broadcast_Block_North_Value	0x0000034078	32	roRead-only	0x00000000	Current value of block for broadcast signals to North
Event_Broadcast_Block_East_Set	0x0000034080	32	woWrite-only	0x00000000	Set block of broadcast signals to East
Event_Broadcast_Block_East_Clr	0x0000034084	32	woWrite-only	0x00000000	Clear block of broadcast signals to East
Event_Broadcast_Block_East_Value	0x0000034088	32	roRead-only	0x00000000	Current value of block for broadcast signals to East
Trace_Control0	0x00000340D0	32	rwNormal read/write	0x00000000	Control of Trace
Trace_Control1	0x00000340D4	32	rwNormal read/write	0x00000000	Control of Trace: packet destination
Trace_Status	0x00000340D8	32	roRead-only	0x00000000	Status of trace engine
Trace_Event0	0x00000340E0	32	rwNormal read/write	0x00000000	Control of which Internal Event to Trace
Trace_Event1	0x00000340E4	32	rwNormal read/write	0x00000000	Control of which Internal Event to Trace
Timer_Trig_Event_Low_Value	0x00000340F0	32	rwNormal read/write	0xFFFFFFFF	Internal Timer Event Value.
Timer_Trig_Event_High_Value	0x00000340F4	32	rwNormal read/write	0xFFFFFFFF	Internal Timer Event Value.
Timer_Low	0x00000340F8	32	roRead-only	0x00000000	Internal Timer Low part Value.
Timer_High	0x00000340FC	32	roRead-only	0x00000000	Internal Timer High part Value.
Event_Status0	0x0000034200	32	wtcReadable, write a 1 to clear	0x00000002	Internal event status register0
Event_Status1	0x0000034204	32	wtcReadable, write a 1 to clear	0x00000000	Internal event status register1
Event_Status2	0x0000034208	32	wtcReadable, write a 1 to clear	0x00000000	Internal event status register2
Event_Status3	0x000003420C	32	wtcReadable, write a 1 to clear	0x00000000	Internal event status register3
Combo_event_inputs	0x0000034400	32	rwNormal read/write	0x00000000	Combo events input events
Combo_event_control	0x0000034404	32	rwNormal read/write	0x00000000	Combo events input events
Event_Group_0_Enable	0x0000034500	32	rwNormal read/write	0x000003FF	Event enable for Group 0
Event_Group_PC_Enable	0x0000034504	32	rwNormal read/write	0x0000003F	Event enable for PC Group
Event_Group_Core_Stall_Enable	0x0000034508	32	rwNormal read/write	0x000001FF	Event enable for AI Engine Stall Group
Event_Group_Core_Program_Flow_Enable	0x000003450C	32	rwNormal read/write	0x00001FFF	Event enable for AI Engine Program Flow Group
Event_Group_Errors0_Enable	0x0000034510	32	rwNormal read/write	0x003FFFFF	Event enable for Non Fatal Error Group
Event_Group_Errors1_Enable	0x0000034514	32	rwNormal read/write	0x003FFFFF	Event enable for AI Engine Fatal Error Group
Event_Group_Stream_Switch_Enable	0x0000034518	32	rwNormal read/write	0xFFFFFFFF	Event enable for Stream Switch Group
Event_Group_Broadcast_Enable	0x000003451C	32	rwNormal read/write	0x0000FFFF	Event enable for Broadcast group
Event_Group_User_Event_Enable	0x0000034520	32	rwNormal read/write	0x0000000F	Event enable for User group
Tile_Control	0x0000036030	32	rwNormal read/write	0x00000000	Tile control register
Tile_Control_Packet_Handler_Status	0x0000036034	32	wtcReadable, write a 1 to clear	0x00000000	Status of control packet handling
Tile_Clock_Control	0x0000036040	32	rwNormal read/write	0x00000003	Clock control for the tile
Stream_Switch_Master_Config_AIE0	0x000003F000	32	rwNormal read/write	0x00000000	Stream Switch Master Configuration AI Engine 0
Stream_Switch_Master_Config_AIE1	0x000003F004	32	rwNormal read/write	0x00000000	Stream Switch Master Configuration AI Engine 1
Stream_Switch_Master_Config_DMA0	0x000003F008	32	rwNormal read/write	0x00000000	Stream Switch Master Configuration DMA 0
Stream_Switch_Master_Config_DMA1	0x000003F00C	32	rwNormal read/write	0x00000000	Stream Switch Master Configuration DMA 1
Stream_Switch_Master_Config_Tile_Ctrl	0x000003F010	32	rwNormal read/write	0x00000000	Stream Switch Master Configuration AI Engine Tile Ctrl
Stream_Switch_Master_Config_FIFO0	0x000003F014	32	rwNormal read/write	0x00000000	Stream Switch Master Configuration FIFO 0
Stream_Switch_Master_Config_FIFO1	0x000003F018	32	rwNormal read/write	0x00000000	Stream Switch Master Configuration FIFO 1
Stream_Switch_Master_Config_South0	0x000003F01C	32	rwNormal read/write	0x00000000	Stream Switch Master Configuration South 0
Stream_Switch_Master_Config_South1	0x000003F020	32	rwNormal read/write	0x00000000	Stream Switch Master Configuration South 1
Stream_Switch_Master_Config_South2	0x000003F024	32	rwNormal read/write	0x00000000	Stream Switch Master Configuration South 2
Stream_Switch_Master_Config_South3	0x000003F028	32	rwNormal read/write	0x00000000	Stream Switch Master Configuration South 3
Stream_Switch_Master_Config_West0	0x000003F02C	32	rwNormal read/write	0x00000000	Stream Switch Master Configuration West 0
Stream_Switch_Master_Config_West1	0x000003F030	32	rwNormal read/write	0x00000000	Stream Switch Master Configuration West 1
Stream_Switch_Master_Config_West2	0x000003F034	32	rwNormal read/write	0x00000000	Stream Switch Master Configuration West 2
Stream_Switch_Master_Config_West3	0x000003F038	32	rwNormal read/write	0x00000000	Stream Switch Master Configuration West 3
Stream_Switch_Master_Config_North0	0x000003F03C	32	rwNormal read/write	0x00000000	Stream Switch Master Configuration North 0
Stream_Switch_Master_Config_North1	0x000003F040	32	rwNormal read/write	0x00000000	Stream Switch Master Configuration North 1
Stream_Switch_Master_Config_North2	0x000003F044	32	rwNormal read/write	0x00000000	Stream Switch Master Configuration North 2
Stream_Switch_Master_Config_North3	0x000003F048	32	rwNormal read/write	0x00000000	Stream Switch Master Configuration North 3
Stream_Switch_Master_Config_North4	0x000003F04C	32	rwNormal read/write	0x00000000	Stream Switch Master Configuration North 4
Stream_Switch_Master_Config_North5	0x000003F050	32	rwNormal read/write	0x00000000	Stream Switch Master Configuration North 5
Stream_Switch_Master_Config_East0	0x000003F054	32	rwNormal read/write	0x00000000	Stream Switch Master Configuration East 0
Stream_Switch_Master_Config_East1	0x000003F058	32	rwNormal read/write	0x00000000	Stream Switch Master Configuration East 1
Stream_Switch_Master_Config_East2	0x000003F05C	32	rwNormal read/write	0x00000000	Stream Switch Master Configuration East 2
Stream_Switch_Master_Config_East3	0x000003F060	32	rwNormal read/write	0x00000000	Stream Switch Master Configuration East 3
Stream_Switch_Slave_AIE0_Config	0x000003F100	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration AI Engine 0
Stream_Switch_Slave_AIE1_Config	0x000003F104	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration AI Engine 1
Stream_Switch_Slave_DMA_0_Config	0x000003F108	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration DMA 0
Stream_Switch_Slave_DMA_1_Config	0x000003F10C	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration DMA 1
Stream_Switch_Slave_Tile_Ctrl_Config	0x000003F110	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration Tile Ctrl
Stream_Switch_Slave_FIFO_0_Config	0x000003F114	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration FIFO 0
Stream_Switch_Slave_FIFO_1_Config	0x000003F118	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration FIFO 1
Stream_Switch_Slave_South_0_Config	0x000003F11C	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration South 0
Stream_Switch_Slave_South_1_Config	0x000003F120	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration South 1
Stream_Switch_Slave_South_2_Config	0x000003F124	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration South 2
Stream_Switch_Slave_South_3_Config	0x000003F128	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration South 3
Stream_Switch_Slave_South_4_Config	0x000003F12C	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration South 4
Stream_Switch_Slave_South_5_Config	0x000003F130	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration South 5
Stream_Switch_Slave_West_0_Config	0x000003F134	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration West 0
Stream_Switch_Slave_West_1_Config	0x000003F138	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration West 1
Stream_Switch_Slave_West_2_Config	0x000003F13C	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration West 2
Stream_Switch_Slave_West_3_Config	0x000003F140	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration West 3
Stream_Switch_Slave_North_0_Config	0x000003F144	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration North 0
Stream_Switch_Slave_North_1_Config	0x000003F148	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration North 1
Stream_Switch_Slave_North_2_Config	0x000003F14C	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration North 2
Stream_Switch_Slave_North_3_Config	0x000003F150	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration North 3
Stream_Switch_Slave_East_0_Config	0x000003F154	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration East 0
Stream_Switch_Slave_East_1_Config	0x000003F158	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration East 1
Stream_Switch_Slave_East_2_Config	0x000003F15C	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration East 2
Stream_Switch_Slave_East_3_Config	0x000003F160	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration East 3
Stream_Switch_Slave_AIE_Trace_Config	0x000003F164	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration AI Engine Trace
Stream_Switch_Slave_Mem_Trace_Config	0x000003F168	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration Mem Trace
Stream_Switch_Slave_AIE0_Slot0	0x000003F200	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration AI Engine 0
Stream_Switch_Slave_AIE0_Slot1	0x000003F204	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration AI Engine 0
Stream_Switch_Slave_AIE0_Slot2	0x000003F208	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration AI Engine 0
Stream_Switch_Slave_AIE0_Slot3	0x000003F20C	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration AI Engine 0
Stream_Switch_Slave_AIE1_Slot0	0x000003F210	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration AI Engine 1
Stream_Switch_Slave_AIE1_Slot1	0x000003F214	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration AI Engine 1
Stream_Switch_Slave_AIE1_Slot2	0x000003F218	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration AI Engine 1
Stream_Switch_Slave_AIE1_Slot3	0x000003F21C	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration AI Engine 1
Stream_Switch_Slave_DMA_0_Slot0	0x000003F220	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration DMA 0
Stream_Switch_Slave_DMA_0_Slot1	0x000003F224	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration DMA 0
Stream_Switch_Slave_DMA_0_Slot2	0x000003F228	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration DMA 0
Stream_Switch_Slave_DMA_0_Slot3	0x000003F22C	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration DMA 0
Stream_Switch_Slave_DMA_1_Slot0	0x000003F230	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration DMA 1
Stream_Switch_Slave_DMA_1_Slot1	0x000003F234	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration DMA 1
Stream_Switch_Slave_DMA_1_Slot2	0x000003F238	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration DMA 1
Stream_Switch_Slave_DMA_1_Slot3	0x000003F23C	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration DMA 1
Stream_Switch_Slave_Tile_Ctrl_Slot0	0x000003F240	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration Tile Ctrl
Stream_Switch_Slave_Tile_Ctrl_Slot1	0x000003F244	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration Tile Ctrl
Stream_Switch_Slave_Tile_Ctrl_Slot2	0x000003F248	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration Tile Ctrl
Stream_Switch_Slave_Tile_Ctrl_Slot3	0x000003F24C	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration Tile Ctrl
Stream_Switch_Slave_FIFO_0_Slot0	0x000003F250	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration FIFO 0
Stream_Switch_Slave_FIFO_0_Slot1	0x000003F254	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration FIFO 0
Stream_Switch_Slave_FIFO_0_Slot2	0x000003F258	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration FIFO 0
Stream_Switch_Slave_FIFO_0_Slot3	0x000003F25C	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration FIFO 0
Stream_Switch_Slave_FIFO_1_Slot0	0x000003F260	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration FIFO 1
Stream_Switch_Slave_FIFO_1_Slot1	0x000003F264	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration FIFO 1
Stream_Switch_Slave_FIFO_1_Slot2	0x000003F268	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration FIFO 1
Stream_Switch_Slave_FIFO_1_Slot3	0x000003F26C	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration FIFO 1
Stream_Switch_Slave_South_0_Slot0	0x000003F270	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration South 0
Stream_Switch_Slave_South_0_Slot1	0x000003F274	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration South 0
Stream_Switch_Slave_South_0_Slot2	0x000003F278	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration South 0
Stream_Switch_Slave_South_0_Slot3	0x000003F27C	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration South 0
Stream_Switch_Slave_South_1_Slot0	0x000003F280	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration South 1
Stream_Switch_Slave_South_1_Slot1	0x000003F284	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration South 1
Stream_Switch_Slave_South_1_Slot2	0x000003F288	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration South 1
Stream_Switch_Slave_South_1_Slot3	0x000003F28C	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration South 1
Stream_Switch_Slave_South_2_Slot0	0x000003F290	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration South 2
Stream_Switch_Slave_South_2_Slot1	0x000003F294	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration South 2
Stream_Switch_Slave_South_2_Slot2	0x000003F298	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration South 2
Stream_Switch_Slave_South_2_Slot3	0x000003F29C	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration South 2
Stream_Switch_Slave_South_3_Slot0	0x000003F2A0	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration South 3
Stream_Switch_Slave_South_3_Slot1	0x000003F2A4	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration South 3
Stream_Switch_Slave_South_3_Slot2	0x000003F2A8	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration South 3
Stream_Switch_Slave_South_3_Slot3	0x000003F2AC	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration South 3
Stream_Switch_Slave_South_4_Slot0	0x000003F2B0	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration South 4
Stream_Switch_Slave_South_4_Slot1	0x000003F2B4	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration South 4
Stream_Switch_Slave_South_4_Slot2	0x000003F2B8	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration South 4
Stream_Switch_Slave_South_4_Slot3	0x000003F2BC	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration South 4
Stream_Switch_Slave_South_5_Slot0	0x000003F2C0	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration South 5
Stream_Switch_Slave_South_5_Slot1	0x000003F2C4	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration South 5
Stream_Switch_Slave_South_5_Slot2	0x000003F2C8	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration South 5
Stream_Switch_Slave_South_5_Slot3	0x000003F2CC	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration South 5
Stream_Switch_Slave_West_0_Slot0	0x000003F2D0	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration West 0
Stream_Switch_Slave_West_0_Slot1	0x000003F2D4	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration West 0
Stream_Switch_Slave_West_0_Slot2	0x000003F2D8	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration West 0
Stream_Switch_Slave_West_0_Slot3	0x000003F2DC	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration West 0
Stream_Switch_Slave_West_1_Slot0	0x000003F2E0	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration West 1
Stream_Switch_Slave_West_1_Slot1	0x000003F2E4	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration West 1
Stream_Switch_Slave_West_1_Slot2	0x000003F2E8	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration West 1
Stream_Switch_Slave_West_1_Slot3	0x000003F2EC	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration West 1
Stream_Switch_Slave_West_2_Slot0	0x000003F2F0	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration West 2
Stream_Switch_Slave_West_2_Slot1	0x000003F2F4	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration West 2
Stream_Switch_Slave_West_2_Slot2	0x000003F2F8	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration West 2
Stream_Switch_Slave_West_2_Slot3	0x000003F2FC	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration West 2
Stream_Switch_Slave_West_3_Slot0	0x000003F300	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration West 3
Stream_Switch_Slave_West_3_Slot1	0x000003F304	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration West 3
Stream_Switch_Slave_West_3_Slot2	0x000003F308	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration West 3
Stream_Switch_Slave_West_3_Slot3	0x000003F30C	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration West 3
Stream_Switch_Slave_North_0_Slot0	0x000003F310	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration North 0
Stream_Switch_Slave_North_0_Slot1	0x000003F314	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration North 0
Stream_Switch_Slave_North_0_Slot2	0x000003F318	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration North 0
Stream_Switch_Slave_North_0_Slot3	0x000003F31C	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration North 0
Stream_Switch_Slave_North_1_Slot0	0x000003F320	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration North 1
Stream_Switch_Slave_North_1_Slot1	0x000003F324	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration North 1
Stream_Switch_Slave_North_1_Slot2	0x000003F328	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration North 1
Stream_Switch_Slave_North_1_Slot3	0x000003F32C	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration North 1
Stream_Switch_Slave_North_2_Slot0	0x000003F330	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration North 2
Stream_Switch_Slave_North_2_Slot1	0x000003F334	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration North 2
Stream_Switch_Slave_North_2_Slot2	0x000003F338	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration North 2
Stream_Switch_Slave_North_2_Slot3	0x000003F33C	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration North 2
Stream_Switch_Slave_North_3_Slot0	0x000003F340	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration North 3
Stream_Switch_Slave_North_3_Slot1	0x000003F344	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration North 3
Stream_Switch_Slave_North_3_Slot2	0x000003F348	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration North 3
Stream_Switch_Slave_North_3_Slot3	0x000003F34C	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration North 3
Stream_Switch_Slave_East_0_Slot0	0x000003F350	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration East 0
Stream_Switch_Slave_East_0_Slot1	0x000003F354	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration East 0
Stream_Switch_Slave_East_0_Slot2	0x000003F358	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration East 0
Stream_Switch_Slave_East_0_Slot3	0x000003F35C	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration East 0
Stream_Switch_Slave_East_1_Slot0	0x000003F360	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration East 1
Stream_Switch_Slave_East_1_Slot1	0x000003F364	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration East 1
Stream_Switch_Slave_East_1_Slot2	0x000003F368	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration East 1
Stream_Switch_Slave_East_1_Slot3	0x000003F36C	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration East 1
Stream_Switch_Slave_East_2_Slot0	0x000003F370	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration East 2
Stream_Switch_Slave_East_2_Slot1	0x000003F374	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration East 2
Stream_Switch_Slave_East_2_Slot2	0x000003F378	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration East 2
Stream_Switch_Slave_East_2_Slot3	0x000003F37C	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration East 2
Stream_Switch_Slave_East_3_Slot0	0x000003F380	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration East 3
Stream_Switch_Slave_East_3_Slot1	0x000003F384	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration East 3
Stream_Switch_Slave_East_3_Slot2	0x000003F388	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration East 3
Stream_Switch_Slave_East_3_Slot3	0x000003F38C	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration East 3
Stream_Switch_Slave_AIE_Trace_Slot0	0x000003F390	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration AI Engine Trace
Stream_Switch_Slave_AIE_Trace_Slot1	0x000003F394	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration AI Engine Trace
Stream_Switch_Slave_AIE_Trace_Slot2	0x000003F398	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration AI Engine Trace
Stream_Switch_Slave_AIE_Trace_Slot3	0x000003F39C	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration AI Engine Trace
Stream_Switch_Slave_Mem_Trace_Slot0	0x000003F3A0	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration Mem Trace
Stream_Switch_Slave_Mem_Trace_Slot1	0x000003F3A4	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration Mem Trace
Stream_Switch_Slave_Mem_Trace_Slot2	0x000003F3A8	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration Mem Trace
Stream_Switch_Slave_Mem_Trace_Slot3	0x000003F3AC	32	rwNormal read/write	0x00000000	Stream Switch Slave Configuration Mem Trace
Stream_Switch_Event_Port_Selection_0	0x000003FF00	32	rwNormal read/write	0x00000000	Select Stream Switch Ports for event generation
Stream_Switch_Event_Port_Selection_1	0x000003FF04	32	rwNormal read/write	0x00000000	Select Stream Switch Ports for event generation