Stream_Switch_Slave_West_2_Config (AIE_CORE_MODULE) Register

Versal Adaptive SoC AI Engine Register Reference (AM015)

Document ID
AM015
Release Date
2024-04-12
Revision
1.2

Stream_Switch_Slave_West_2_Config (AIE_CORE_MODULE) Register Description

Register NameStream_Switch_Slave_West_2_Config
Offset Address0x000003F13C
Absolute Address For calculated base addresses for each device, see Answer Record 000036195.
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionStream Switch Slave Configuration West 2

Stream_Switch_Slave_West_2_Config (AIE_CORE_MODULE) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Slave_Enable31rwNormal read/write0x01=enable the slave port
Packet_Enable30rwNormal read/write0x00=circuit; 1=packet switching mode for slave port