HLS Toolbox Based PID Implementation

PID Controller Design with Model Composer for Versal ACAPs (XAPP1376)

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1.0 English

The create and run test bench option in the HLS Toolbox PL implementation VMC auto generates all files necessary to create a Vitis™ HLS project. The following figure is a screen capture from a Vitis HLS PID_project that includes a pass/fail test bench using the Simulink source stimulus.

Figure 1. Generate a Vitis HLS HLS PID_PL Project

VMC auto generates the following Vitis HLS files:

  • A C++ based PID model
  • A test bench
  • A Vitis HLS run_hls.tcl file that creates a project and runs through csim and cosim

Executing the Tcl script from a Vitis HLS command prompt creates a Vitis HLS project. For GUI-based exploration and optimization, the Vitis GUI can be opened. Otherwise, continue with the Tcl script. The resource, achievable clock rate, and latency information for the HLS Toolbox implementation is demonstrated in the following figures where Clock Rate = 1/2.118e–8 = 472 MHz and Sample Rate = 1/(69 × 2.118e–9) = 6.8 MSPS.

Figure 2. Export Report
Figure 3. HLS Toolbox PID Single Precision Floating Point HLS Implementation Results