Reference Design

PID Controller Design with Model Composer for Versal ACAPs (XAPP1376)

Document ID
Release Date
1.0 English

Download the reference design files for this application note from the Xilinx website.

Reference Design Matrix

The following checklist indicates the procedures used for the provided reference design.

Table 1. Reference Design Matrix
Parameter Description
Developer name Mike Mitchell
Target devices Versal ACAPs
Source code provided? Y
Source code format (if provided) Various
Design uses code or IP from existing reference design, application note, 3rd party or Vivado software? If yes, list. Partial reuse from PID Controller Design with Model Composer (XAPP1341)
Functional simulation performed Y
Timing simulation performed? Y
Test bench provided for functional and timing simulation? Y
Test bench format Model Composer
Simulator software and version 2022.1 Xilinx Tools
SPICE/IBIS simulations N
Synthesis software tools/versions used Vivado synthesis
Implementation software tool(s) and version Vivado Implementation
Static timing analysis performed? N
Hardware Verification
Hardware verified? Y
Platform used for verification VCK190

The reference design includes the following files:

  • ClosedLoopPID_ACAP.slx: Single precision floating point PID controller using native VMC blocks, C++ based Math Sequencer, single channel AI Engine designs
  • ClosedLoopPID_ACAP_rv2.slx: Single precision floating point PID controller example for both a single channel and a four channel AI Engine design
  • ms.cpp, ms.h: PL-based Math Sequencer C++ source files
  •,, PID.h: AI Engine C++ source files
  • create_library.m: MATLAB file used to create the C++ simulatable Math Sequencer library block for use in a Simulink design