Emulation AI Engine Analysis

PID Controller Design with Model Composer for Versal ACAPs (XAPP1376)

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VMC gives you the ability to explore Vitis based performance metrics, graph, array, trace, and log details using the Vitis Analyzer GUI.

Figure 1. Vitis Analyzer Results Analysis

All Vitis files generated from a VMC Emulation-AI Engine simulation are available for exploration or reuse as shown in the following figure.

Figure 2. Vitis Emulation-SW and Emulation-AI Engine Directories

A makefile is generated as part of the Emulation-AI Engine simulation in addition to a test bench, AI Engine Adaptive DataFlow graph files (PID_AIE.cpp, PID_AIE.h), and user defined source files. You can execute the VMC created ./code/Work_aiesim/Makefile in order to perform a Vitis Emulation-SW (make all_x86) or a Vitis Emulation-AI Engine (through a Vitis xterm make all) standalone simulation.