AI Engine Hardware Validation

PID Controller Design with Model Composer for Versal ACAPs (XAPP1376)

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AI Engine, AI Engine+RTL, or AI Engine+HLS based designs can be run in the hardware using the Model Composer Hub through the Generate Hardware Image option shown in the following figure.

Figure 1. Generate Hardware Image Option in the VMC Hub

The following figure demonstrates the hardware validation flow as an automated method to verify a working AI Engine hardware-based design where the com port echos the pass/fail sample based results for the four-channel AI Engine design.

Figure 2. Com Port Results from Hardware Validation

To simply change the test bench rather than going through the longer process of recompiling the hardware design, perform the following sequence of events:

  1. Change the test bench.
  2. Use the VMC Hub to re-simulate.

Being able to switch out the test bench without recompiling the hardware can significantly reduce validation for larger simulation vector sets needed to fully vet a design.