This application note and the associated reference designs describe how to construct source synchronous high-speed I/O interfaces using the Advanced I/O Wizard (AIOW) on Versal™ devices. The wizard instantiates and configures I/O and clocking logic, such as XPHY nibbles and XPLL blocks, that are included in the physical-side interface (PHY) architecture. The designs in this application note are not hardware tested, but are verified through behavioral simulation.
Download the reference design files from the Xilinx® website. For detailed information about the design files, see the single-bank source synchronous design Reference Design section and the multi-bank source synchronous design Reference Design section.