Download the reference design files from the Xilinx website. Unzip this file and browse into the top-level folder xapp1350. Check the Multi_Bank_Ssync_Loopback_Design folder, which has all the source files under Sources, Constraints, and Testbench.
Folder | File Name | Description |
---|---|---|
Sources | toplevel_mb.sv | The top-level design file that instantiates the TX and RX cores and connects the design |
Prbs_RxTx.vhd | Outer wrapper for the custom PRBS generator and checker | |
Prbs_Any.vhd | Contains the modules for the PRBS generator and checker | |
Constraints | toplevel_mb.xdc | The constraints file to assign pin locations to ports of the design for all bank instances and set the necessary attributes for bank instance 0 (Default bank instance) |
attributes_mb.xdc | The constraints file to set the attributes for bank instances 1 and 2 (Non-default bank instances). This file is marked to be used only for post optimization. | |
Test Bench | toplevel_testbench_mb.sv | The top-level test bench file to test the design |
toplevel_testbench_behav.wcfg | Waveform configuration file |
Reference Design Matrix
The following checklist indicates the procedures used for the provided reference design.
Parameter | Description |
---|---|
General | |
Developer name | Xilinx |
Target devices | Versal ACAP |
Source code provided? | Yes |
Source code format (if provided) | Verilog and VHDL |
Design uses code or IP from existing reference design, application note, 3rd party or Vivado software? If yes, list. | Yes. Uses the Advanced I/O Wizard from the IP catalog. |
Simulation | |
Functional simulation performed | Yes |
Timing simulation performed? | No |
Test bench provided for functional and timing simulation? | Yes |
Test bench format | Verilog |
Simulator software and version | Vivado simulator 2020.1 |
SPICE/IBIS simulations | No |
Implementation | |
Synthesis software tools/versions used | Vivado synthesis 2020.1 |
Implementation software tool(s) and version | Vivado 2020.1 implementation |
Static timing analysis performed? | Yes |
Hardware Verification | |
Hardware verified? | No |
Platform used for verification | N/A |