In the multi-bank source synchronous reference design, all three available banks are used, which is the maximum width of a single I/O interface supported by the AIOW. This design uses all nine XPHY nibbles from one XPIO bank, with each XPHY nibble containing six XPHY NIBBLESLICEs that transmit and receive data from six individual I/O pins, for a total of 54 pins/bank. This design has three banks, and consequently, uses a total of 27 XPHY nibbles. The wizard requires the banks to be adjacent to each other. The transmit clock can be forwarded from the transmit core either via the clock forward pins or the transmit data pins from the bank. In the reference design, the transmit clock is forwarded via the transmit data pins. The design uses the LVDS standard for the I/Os, and consequently, the data, transmit/capture clock, and PLL input clock use differential I/O pin pairs.
The wizard configures clocking circuitry using the XPLL that is needed to support these configurations. In this design, the XPLL is instantiated in the core and the wizard configures the XPLL clock frequencies. The XPLL input clock is fed through a global clock (GC) input pin. As a result, the core reserves a pair of I/Os for the PLL input clock for RX, one pair of I/Os for the capture clock, and the remainder for the data in each bank. Consequently, the transmit and receive cores have 25 pairs for data transmission and reception per bank. See Advanced I/O Wizard LogiCORE IP Product Guide (PG320) for more information on the AIOW. Each bank has a transmit clock of its own that the transmitter transmits. Similarly, the receiver receives a capture clock on each bank.
Clocking in the multi-bank source synchronous reference design is similar to the single-bank design. Instead of one instantiation of the XPLL as in the single-bank design, this design has three instantiations of the XPLLs, one for each bank. A common PLL input clock for all the XPLLs is fed into the RX core via the clock capable pins. This clock drives the CLKIN of the XPLLs for each bank. The TX core has three separate inputs for the PLL input clock, which is fed to the bank<0/1/2>_pll_clkin ports of the TX core. It uses the same clock as the RX core except that it passes through an IBUFDS to create a single-ended version that is passed to the respective CLKIN ports of each bank on the TX core.
In this design, the TX core uses the "Fabric (driven by BUFG)" option as the PLL clock source in the AIOW. These clocks are received on the GC pins and, consequently, do not need any BUFGs added with the IBUFDS. The clocks need BUFGs added with the IBUFDS if they are not received on the GC pins. The following figures illustrate how the clocks are connected to the TX and RX cores, respectively.
The reference design uses the PRBS generator and checker to exercise the I/Os.
The design files for the PRBS generator and checker are provided in the design suite. It
is instantiated in the top-level source file. The PRBS generator generates the data and
feeds the TX core, which serializes it and transmits to the RX core via external
loopback. The RX core feeds the data to the PRBS checker after deserializing it. It
flags if it detects any mismatch. The block diagram of the reference design is shown in
the following figure. The transmit clock or strobe is generated by feeding the pattern
01010101 to the corresponding TX NIBBLESLICEs for
each bank.
