This RX core is set up to work for a data rate of 1800 Mb/s. Also, the core is configured for LVDS15 in the reference design. This multi-bank design uses a clock capable pin as a PLL clock source and is configured for an edge aligned DDR system. An XPIO bank has 54 pins and the design uses all 54 pins in the form of 25 pairs of data pins, one pair for capture clock, and one pair of PLL input clock, in the bank receiving the input clock. The other two banks use 52 pins in the form of 25 pairs of data pins and one pair for capture clock. The PLL input clock is received by the core and then forwarded to all of the three instantiations of the XPLLs. The wizard allocates one XPLL per bank. The design constrains the ports for the receive interfaces and the wizard takes care of the placement.